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same input output signal name in simulink

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TaeHee Kwun
TaeHee Kwun on 12 Jul 2019
Commented: TaeHee Kwun on 20 Jul 2019
I want to make code below by model (or stateflow) using Code Generation
if( var > 10){
var = 10;
}
In this case, upper 'var' is input of chart(or subsystem) and lower 'var' is output of chart.
So, it occurs signal complication if I use same variables name or I can't make same name of chart's input and output.
I can make this if sentance by using two variables, but I hope to make this by using one.
Thanks for your help.
Sincerely,
TaeHee Kwun.

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Accepted Answer

Phani Teja
Phani Teja on 16 Jul 2019
Edited: Phani Teja on 16 Jul 2019
Yeh It can be possible with Data store memory block.
Make a Variable 'Var' in stateflow and change its scope to Data store memory .
You can also control the variable storage class by resolving data store memory with simulink signal.
The generated code looks like:
/* Real-time model */
RT_MODEL_Chart_T Chart_M_;
RT_MODEL_Chart_T *const Chart_M = &Chart_M_;
/* Model step function */
void Chart_step(void)
{
/* Chart: '<Root>/Chart' */
/* Re-use inputs */
if (Var > 10) {
/* NEW_PATTERN */
Var = 10;
}
/* End of Chart: '<Root>/Chart' */
}

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TaeHee Kwun
TaeHee Kwun on 20 Jul 2019
Thanks for your answer!
But, I can't still understand how to make this blocks...
If you can, can you upload some of your blocks?
Thanks.

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