- To set up a synthesis tool using "hdlsetuptoolpath", see the following documentation: https://www.mathworks.com/help/hdlcoder/gs/toolbox-setup.html
- To see the list of all supported synthesis tools for HDL Coder for the current release, see the following documentation: https://www.mathworks.com/help/hdlcoder/gs/language-and-tool-version-support.html#bs7w74k-1
- Here is the complete list of supported Xilinx Vivado versions for each MATLAB release: https://www.mathworks.com/matlabcentral/answers/518421-which-versions-of-xilinx-vivado-are-supported-with-which-release-of-hdl-coder/
Do I have to install a third-party synthesis tool to use HDL Coder?
2 views (last 30 days)
Show older comments
MathWorks Support Team
on 30 Mar 2021
Edited: MathWorks Support Team
on 4 Mar 2024
Do I have to install a third-party HDL synthesis tool (e.g. Xilinx Vivado, Altera/Intel Quartus, Microsemi Libero) to use HDL Coder and its support packages?
Accepted Answer
MathWorks Support Team
on 9 May 2024
Edited: MathWorks Support Team
on 4 Mar 2024
This will depend on the workflow that you select in HDL Workflow Advisor step 1.1.:
(1) IP Core Generation, FPGA-in-the-loop, FPGA Turnkey, Simulink Real-Time FPGA I/O
When using the above workflows in HDL Workflow Advisor, HDL Coder expects that you have a third-party synthesis tool (appropriate for your FPGA) available.
This is because these workflows are tailored to work on specific FPGA devices and supported evaluation boards for which we provide HDL Coder support packages.
The synthesis tool can be installed on the computer running MATLAB/Simulink, or on a network/server location that is accessible from your computer. You will be prompted to set up your synthesis tool for use with MATLAB when installing an HDL Coder support package.
(2) Generic ASIC/FPGA
Only for the "Generic ASIC/FPGA" target workflow, the presence of a synthesis tool is optional. An exception to this is if you configured MATLAB/Simulink to include vendor-specific code, such as floating-point libraries.
In general, HDL Coder has the ability to generate portable, platform-independent HDL code from your MATLAB function or Simulink model. If you do not want to invoke a synthesis tool from MATLAB/Simulink, and would rather like to integrate the generated VHDL/Verilog code into your FPGA project manually, see the following answer on generating HDL code only:
https://www.mathworks.com/matlabcentral/answers/1643865-how-do-i-generate-code-only-with-hdl-coder0 Comments
More Answers (0)
See Also
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!