In VHDL or Verilog, Can any one let me know how to implement 1) for loop , 2) nested for loop 3) RAM or ROM of desired size , thanking you in aticipation

In VHDL/Verilog architecture how to implement 1) for loop , 2) nested for loop, 3) RAM or ROM of desired size

thanking you in advance

Answer 1

[Tim McBrayer]

It seems as if you are asking basic HDL language questions. if so, this is the wrong venue to look for such answers.

If you are referring to VHDL/Verilog code generation from MATLAB or Simulink, and how to generate the named constructs, the answers are all in the documentation. You write for loops directly in your MATLAB code. For a MATLAB based RAM, simply declare a persistent array of the suitable size. For a Simulink RAM, use a RAM block with the desired interface.