![photo](/responsive_image/150/150/0/0/0/cache/matlabcentral/profiles/20858817_1622202763503_DEF.jpg)
Angela Cuadros Castiblanco
Followers: 0 Following: 0
English, Spanish
Statistics
0 Questions
4 Answers
RANK
7,559
of 293,530
REPUTATION
6
CONTRIBUTIONS
0 Questions
4 Answers
ANSWER ACCEPTANCE
0.00%
VOTES RECEIVED
1
RANK
of 20,040
REPUTATION
N/A
AVERAGE RATING
0.00
CONTRIBUTIONS
0 Files
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANK
of 148,733
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Highlights
AVERAGE NO. OF LIKES
Feeds
simulink ip core generation
Hello, To use the AXI4-Stream interface in the IP core generation workflow in HDL Coder, you can model your algorithm to operat...
4 months ago | 0
AXI-stream interface violates AXI-stream protocol
Hello Alexander, I'd like to provide some clarity on the protocol implementation within our IP core generation workflow. When m...
8 months ago | 0
Setting Target interface fails in Debug Zynq design using HDL and Embedded coder example.
Hello Vishnu, The error message you're seeing typically appears when a reference design requires certain non-optional interfac...
10 months ago | 1
HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
Hello, From your description it sounds like you are using the "legacy frame-based modeling" detailed in: https://www.mathwor...
1 year ago | 0
| accepted