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shreyas


Indian Institute of Technology

Active since 2012

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HDL Verifier and FPGA in the loop
Hello All, I am trying to use FPGA in the Loop (FIL) using HDL verifier and simulink, but I keep getting the error: Did no...

11 years ago | 8 answers | 2

8

answers

Question


EDA Simulator link and Simulink Cosimulation
Hello All, I am trying to use EDA simulator link with simulink but I am getting the error: Error reported by S...

12 years ago | 3 answers | 0

3

answers