Alexander Kiermayer

Active since 2016

Followers: 0 Following: 0

Message

Answered
Using Unit Delays in triggered Subsystems for HDL Codegeneration
I solved the problem. I had a Limited Counter for triggering the subsystem. After replacing it by an HDL counter, everything i...

6 years ago | 0

| accepted

Question

Using Unit Delays in triggered Subsystems for HDL Codegeneration
Hi, i'm having some Unit Delays in a Triggered Subsystem. When generating VHDL Code using Mathworks HDL Coder I get the foll...

6 years ago | 2 answers | 0

answers

Question

HDL Coder generates VHD Files for Sample and Hold Blocks
Hi, I'm using Sample and Hold Blocks in my design. When I generate the VHDL Code, I get files named like "controlss_block.vhd"...

7 years ago | 1 answer | 0

answer