ETRI Accelerates Radar Emulations by Running Algorithms on NI FPGAs
New Workflow Reduces Time and Effort to Implement HDL Code by 50%
“It is especially helpful that most of the main algorithm code can be used as is without any additional work using MATLAB Function blocks. Even with no HDL expertise, it was easy to convert the algorithm to HDL code using HDL Coder.”
Key Outcomes
- Time and effort required to implement HDL code was reduced by 50% compared to traditional workflows involving handwritten code or other design methods
- Verification effort was reduced by 50% by using cosimulation to compare the behavior of the algorithm and generated HDL code
- Real-time signal processing of the target FPGA enabled behavioral verification and performance testing on the system level
HDL code generation gave ETRI a matched design of the algorithm (top) and the HDL model (bottom).
The Electronics and Telecommunications Research Institute (ETRI) is a leader in Korea’s information and communications technology. The company’s Radio Research Division used MATLAB® to develop a real-time transmit/receive signal processing module for a low-power radar testbed. However, its execution on a CPU using a third-party graphical programming environment did not meet project requirements. In particular, parallel processing algorithms such as matched filter banks to reduce signal interference required real-time execution, and orthogonal signal receivers had to be implemented in a pipelined structure.
The ETRI team therefore deemed moving to an NI™ FPGA necessary to reach their goals. Directly converting the MATLAB algorithm to HDL was out of the question, as the code would need to be modified manually after each change to the algorithm. Additionally, debugging was challenging because the algorithm’s structure would not be identically reflected in the HDL code.
So, to continue using their IP and the examples and support provided by MathWorks, the team first converted the algorithm to Simulink®, then generated HDL using HDL Coder™. The tradeoffs of different design options for implementation, hardware architecture, and fixed-point data types were easy to assess this way. The algorithm and hardware designers were able to collaborate using cosimulation, reducing iterations between engineers and minimizing repetition and human error.
Beyond this, this workflow provided ETRI engineers with a matched design and verification process where the Simulink model and HDL code had the exact same structure. Using HDL Verifier™ allowed real-time behavioral verification and performance testing at the system level. Through automation, this workflow saved about 50% of the time and effort for both HDL code implementation and real-time behavioral verification. Future projects, such as those involving machine learning–based algorithms, are also expected to use code generation with HDL Coder.
