Generate SystemVerilog DPI
Generate SystemVerilog DPI components from MATLAB functions or Simulink subsystems for use in functional verification environments including Synopsys VCS, Cadence Xcelium, and ModelSim or Questa from Siemens EDA.
Access on-board memory from MATLAB and Simulink over JTAG, Ethernet, or PCI Express. Test FPGA algorithms via read or write access to AXI registers and transfer large image or signal files between MATLAB and Simulink and on-board memory locations.
“Simulink allows for us to reduce time spent on hand-writing production UVM test benches, test sequences and scoreboards by about 50% – leaving more time for us to focus on application for breakthrough innovations. Our ASICs designed for automotive applications rely on UVM for production verification – MATLAB and Simulink simplify the once tedious task of developing the algorithms for these devices.”Khalid Chishti, Allegro MicroSystems