Generate UVM Environments
Use ASIC Testbench to generate complete Universal Verification Methodology (UVM) testbenches from Simulink models. Generate UVM sequences, scoreboards, and predictors, and then incorporate them into production testbenches based on Questa, Xcelium, VCS, or the Vivado simulator.
Generate SystemC TLM 2.0 compatible transaction-level models
Use ASIC Testbench to generate SystemC virtual prototype models with TLM 2.0 interfaces for use in virtual platform simulations. Use TLM generator to produce IP-XACT files with mapping information between Simulink and generated TLM components.
“Simulink allows for us to reduce time spent on hand-writing production UVM test benches, test sequences and scoreboards by about 50% – leaving more time for us to focus on application for breakthrough innovations. Our ASICs designed for automotive applications rely on UVM for production verification – MATLAB and Simulink simplify the once tedious task of developing the algorithms for these devices.”Khalid Chishti, Allegro MicroSystems