Top-Down FPGA and ASIC Design and Verification with MATLAB and Simulink

Model-Based Design with MATLAB^® and Simulink^® provides a collaboration platform to effectively bridge algorithm development to FPGA/ASIC hardware implementation.

Read these papers and watch video tutorials to learn about:

Model-based mixed-signal ASIC design flow
Algorithm to RTL design and verification
ASIC and FPGA workflow for IEC certification
Verification with SystemVerilog DPI generation

Why Adopting a MATLAB and Simulink Workflow Matters

Improve RTL Verification by Connecting to MATLAB

5G NR HDL Cell Search and MIB Recovery Reference Application

A Mixed-Signal Model-Based Design Flow for Automotive Sensors

How to Get Started

Adopting Model-Based Design for FPGA, ASIC, and SoC Development

Generate SystemVerilog DPI for Analog Mixed-Signal Verification

ASIC and FPGA Workflow for ISO 26262 and IEC 61508 (3:06) - Video
How to Use Model-Based Design to Demonstrate DO-254 Compliance (8:25) - Video
Designing a Datapath from an FPGA to a Processor with SoC Blockset (2 videos) - Video Series
Compare FIR Filter Implementations Using socModelAnalyzer - Example
Methodology Guide for Learning and Evaluating HDL Coder - File Exchange

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