Xilinx FPGAs and Zynq SoCs
Model, verify, and program your algorithms on Xilinx devices.
Domain experts and hardware engineers use MATLAB® and Simulink® to develop prototype and production applications for deployment on Xilinx® FPGA and Zynq® SoC devices. With MATLAB and Simulink, you can:
- Model hardware architecture at the system level
- Program your FPGA or SoC without writing any code
- Simulate and debug your FPGA or SoC using MATLAB and Simulink tools
- Perform production FPGA and SoC design
"As a mechatronic systems engineer, my expertise is in control systems and their models, not HDL and FPGAs. With Model-Based Design, I can use my insight and knowledge of the controller and the system being controlled to do more of the work normally done by FPGA engineers and reduce their workload."Rob Reilink, DEMCON
Using MATLAB with Xilinx FPGAs and Zynq SoCs
Modeling for FPGA and SoC Programming
Add hardware architecture to your algorithm using MATLAB and Simulink. This includes fixed-point quantization (30:45), you can use resources more efficiently, and native floating-point (9:19) code generation, so you can more easily program FPGAs. Reuse your tests and golden reference algorithm to simulate each successive refinement.
HDL Coder™ generates synthesizable VHDL or Verilog directly from HDL-ready Simulink and MATLAB function blocks for applications such as signal processing, wireless communications, motor and power control, and image/video processing. Xilinx System Generator for DSP and Xilinx Model Composer add Xilinx-specific blocks to Simulink for system-level simulation and hardware deployment. System Generator blocks can be integrated with native Simulink blocks for HDL code generation.
Analyze the effects of hardware and software architectures for Zynq UltraScale+ MPSoC and RFSoC devices, including the use of memory and scheduling/OS effects, using SoC Blockset™.
- Adopting Model-Based Design for FPGA, ASIC, and SoC Development (15:25)
- Model-Based Design with Simulink, HDL Coder, and Xilinx System Generator for DSP
- Getting Started with the Avnet Ultra96 (4 Videos)
- Software-Defined Radio using MATLAB and Simulink (34:04)
- Designing a Datapath from an FPGA to a Processor with SoC Blockset: Modeling and Simulation (6:11)
Programming Xilinx FPGAs and Zynq SoCs
HDL Coder guides you through the steps to program your FPGA or SoC directly from Simulink without having to write a single line of code. From HDL Coder, you can optimize and generate synthesizable VHDL or Verilog along with AXI interfaces to plug into an SoC. From there you can call Embedded Coder® to generate C/C++ to program the software that runs on the embedded processor.
You can download support packages for Xilinx FPGA and Zynq SoC devices for use with Embedded Coder and HDL Coder. These automate Xilinx Vivado synthesis, place and route, and FPGA/SoC programming. Fully automated workflows are available for supported boards, and address applications such as motor control, video/image processing, and software-defined radio.
FPGA Simulation and Debugging
HDL Verifier™ reuses your MATLAB and Simulink test environments to verify your FPGA design.
With cosimulation (5:35), you can automatically run your MATLAB or Simulink test bench connected to your Verilog or VHDL design running in a simulator from Mentor Graphics or Cadence Design Systems.
Production FPGA and SoC Design
Domain experts and hardware engineers use MATLAB and Simulink to collaborate on production FPGA and SoC design for wireless, image/video processing (20:59), motor and power control (24:20), and safety-critical applications.
HDL Coder high-level synthesis optimizations help you meet your design’s goals while maintaining traceability between the generated RTL, the model, and the requirements, which is important for high-integrity workflows such as DO-254. Along with synthesizable VHDL and Verilog, HDL Coder generates IP cores that easily plug into Vivado IP Integrator for system integration. And HDL Verifier generates verification models (5:19) that help speed test bench development.