Guided Code Generation

Guided code generation using the Configuration Parameters dialog box and Simulink HDL Workflow Advisor

You can generate HDL code for Simulink^® models from the user interface by using the HDL Code tab in the Simulink toolstrip or by using the Configuration Parameters dialog box. In this dialog box, you can specify various HDL code generation settings including basic folder and language selection to more advanced optimization parameters. To learn about how to generate HDL code from the HDL Code tab, see Generate HDL Code from Simulink Model.

To deploy the generated code to a target device, use the Simulink HDL Workflow Advisor. The Advisor can run end-to-end workflows that check HDL compatibility and deploy the generated code to a target device. HDL Workflow Advisor is not available in Simulink Online™.

Functions

`hdladvisor`	Display HDL Workflow Advisor
`hdlsetup`	Set model configuration parameters for HDL code generation
`hdlsetuptoolpath`	Set up system environment to access FPGA synthesis software

Checks

Check for global reset setting for Xilinx and Altera devices

Check algebraic loops

Model Settings

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HDL Code Generation

Generate HDL for	Select subsystem or model for HDL code generation
Language	HDL code generation language
Code Generation Folder	Folder for generated HDL code
Restore Model Defaults	Reset model-level HDL settings to default values
Run Compatibility Checker	Check subsystem compatibility for HDL code generation
Generate	Generate HDL code for subsystem or model

Target

Workflow	Target workflow
Project Folder	Folder for workflow-specific files (Since R2023b)
Target Platform	Platform on which to deploy generated HDL code (Since R2023b)
Synthesis Tool	Synthesis tool to target generated HDL code
Family	Device chip family
Device	Device name
Package	Device package name
Speed	Device speed value
Reference Design	Reference design to integrate with generated IP core (Since R2023b)
Reference Design Tool Version	Option to warn for reference design version mismatch (Since R2023b)
Ignore tool version mismatch	Warning in instances of reference design tool version mismatch (Since R2023b)
Reference Design Parameters	Table of parameters available for default reference designs (Since R2023b)
Target Frequency	Clock frequency for generated HDL design

Optimization

General

Map pipeline delays to RAM	Map pipeline registers in generated HDL code to RAM
RAM mapping threshold	Specify minimum RAM size for mapping to block RAMs
Transform non zero initial value delay	Implement Delay blocks to have zero initial value in generated HDL code
Remove Unused Ports	Remove unused ports from design
Enable-based constraints	Enable multiple clock cycles for data to propagate between registers

Pipelining

Allow design delay distribution	Allow distributed pipelining and delay absorption optimizations to move design delays
Pipeline distribution priority	Priority for distributed pipelining and delay absorption optimizations
Clock-rate pipelining	Insert pipeline registers at faster clock rate than data rate
Allow clock-rate pipelining of DUT output ports	Pass the outputs from DUT at clock rate
Balance clock-rate pipelined DUT output ports	Synchronize DUT outputs while satisfying highest-latency requirements of outputs (Since R2022b)
Distributed pipelining	Enable pipeline register distribution
Use synthesis estimates for distributed pipelining	Use synthesis timing estimates to guide pipeline register insertion (Since R2022a)
Adaptive pipelining	Insert adaptive pipeline registers
Map lookup tables to RAM	Map lookup tables to block RAM (Since R2021b)

Resource Sharing

Share Adders	Share adders with resource sharing optimization
Adder sharing minimum bitwidth	Minimum bit width required to share adders with resource sharing optimization
Share Multipliers	Share multipliers with resource sharing optimization
Multiplier sharing minimum bitwidth	Minimum bit width required to share multipliers with resource sharing optimization
Multiplier promotion threshold	Maximum bitwidth difference for promoting and sharing smaller multipliers
Multiplier partitioning threshold	Maximum input bit width for partitions
Multiply-Add blocks	Share Multiply-Add blocks with resource sharing optimization
Multiply-Add block sharing minimum bitwidth	Minimum bit width required to share Multiply-Add blocks with resource sharing optimization
Atomic subsystems	Share Atomic Subsystem blocks with resource sharing optimization
MATLAB Function blocks	Share MATLAB Function blocks with resource sharing optimization
Floating-Point IPs	Share floating-point IPs with resource sharing optimization

Frame to Sample Conversion

Enable frame to sample conversion	Enable frame-to-sample conversion (Since R2022b)
Samples per cycle	Maximum size of streams for frame-to-sample conversion (Since R2022b)
Input FIFO size	Register size of generated input FIFOs around streaming matrix partitions (Since R2022b)
Output FIFO size	Register size of generated output FIFOs around streaming matrix partitions (Since R2022b)
Input processing order	Processing order to use for frame inputs (Since R2023a)
Delay size threshold for external memory (kilobytes)	Maximum delay size for external memory (Since R2023a)

Floating Point

Use Floating Point	Use native floating-point library (Since R2023a)
Latency Strategy	Specify latency strategy to use for floating-point values
Handle Denormals	Specify whether to handle denormal numbers
Mantissa Multiply Strategy	Specify how to implement mantissa multiplication operation
Vendor Specific Floating Point Library	Select vendor-specific floating-point library (Since R2023a)

Global Settings

Reset type	Reset logic to use for registers in HDL code
Reset asserted level	Active level of reset input signal
Clock input port	Name for clock input port
Clock enable input port	Name for clock enable input port
Reset input port	Name for reset input port
Clock inputs	Generate single or multiple clock inputs
Treat Simulink rates as actual hardware rates	Set oversampling value based on model rates and target frequency values (Since R2023b)
Clock edge	Active clock edge
Oversampling factor	Oversampling value

General

Verilog file extension	File name extension for generated Verilog files
VHDL file extension	File name extension for generated VHDL files
SystemVerilog file extension	File name extension for generated SystemVerilog files (Since R2023b)
Package postfix	Text to append to model or subsystem name
Entity conflict postfix	Text to use to resolve duplicate module names
Split entity file postfix	Text to append to name of generated model file
Reserved word postfix	Text to append to value names, postfix values, or labels
Split arch file postfix	Text to append to name of generated architecture file
Clocked process postfix	Text to append to HDL clock process names
Split entity and architecture	Write architecture code to multiple VHDL files
Complex real part postfix	Text to append to real part of complex signal names
VHDL architecture name	Architecture name for DUT
Complex imaginary part postfix	Text to append to imaginary part of complex signal names
Module name prefix	Text to prefix to module or entity name in generated HDL code
Enable prefix	Base name for internal clock enables and other flow control signals
Timing controller postfix	Text to append to timing controller name
Pipeline postfix	Text to append to names of input or output pipeline registers
VHDL library name	Target library name for generated VHDL code
Generate VHDL or SystemVerilog code for model references into a single library	Generate VHDL or SystemVerilog code in separate libraries
Block generate label	Text to append to HDL `GENERATE` statements
Output generate label	Text to append to assignment blocks in VHDL `GENERATE` statements
Instance generate label	Text to append to instance section labels
Vector prefix	Text to prefix to vector names
Instance prefix	Text to prefix to component instance names
Instance postfix	Text to append to component instance names
Map file postfix	Text to append to generated mapping file

Ports

Input data type	HDL data type for input ports of model
Output data type	HDL data type for output ports of model
Clock enable output port	Name for generated clock enable output port
Minimize clock enables	Omit clock enable logic in generated code
Minimize global resets	Omit reset logic in generated code
Use trigger signal as clock	Use trigger input signal as clock in generated code
Enable HDL DUT input port generation for tunable parameters	Create DUT input ports for tunable parameters (Since R2021b)
Balance delays for generated DUT input ports	Insert matching delays on generated DUT inport port paths (Since R2022b)
Enable HDL DUT output port generation for test points	Create DUT output ports for test point signals
Balance delays for generated DUT output ports	Insert matching delays on generated DUT output port paths (Since R2022b)
Scalarize ports	Flatten vector ports into structure of scalar ports
Max number of I/O pins for FPGA deployment	Maximum number of I/O pins for target FPGA (Since R2022a)
Check for DUT pin count exceeding I/O Threshold	Option to generate error or warning when DUT pin count exceeds maximum number of I/O pins (Since R2023a)

Coding style

Represent constant values by aggregates	Represent constants by using aggregates
Inline MATLAB Function block code	Inline HDL code for MATLAB Function blocks
Initialize all RAM blocks	Generate initial signal value for RAM blocks
RAM Architecture	Specify RAM architecture with or without clock enable
No-reset registers initialization	Specify how to initialize registers that do no reset
Minimize intermediate signals	Minimize intermediate signals in generated code
Unroll For-Generate Loops	Unroll and omit `FOR` and `GENERATE` loops from generated HDL code
Generate parameterized HDL code from masked subsystem	Generate reusable HDL code for subsystems
Enumerated Type Encoding Scheme	Specify encoding scheme to use for enumeration types
Use “rising_edge/falling_edge” style for registers	Use `rising_edge` or `falling_edge` to detect clock transitions in generated code
Code reuse	Specify whether to generate a reusable file for subsystems (Since R2022a)
Inline VHDL configuration	Whether generated VHDL code includes inline configurations
Concatenate type safe zeros	Whether to use type-safe syntax for concatenated zeros in generated VHDL code
Generate obfuscated HDL code	Whether to generate obfuscated HDL code
Preserve Bus structure in the generated HDL code	Generate code with VHDL record or SystemVerilog structure types (Since R2022b)
Indexing for scalarized port naming	Specify starting index for names of scalarized vector ports (Since R2022a)
Optimize timing controller	Generate one counter for each rate in timing controller code
Timing controller architecture	Specify architecture of generated timing controller
Use Verilog or SystemVerilog `timescale directives	Use compiler directives in generated Verilog or SystemVerilog code
Verilog or SystemVerilog timescale specification	Specify timescale to use in generated Verilog or SystemVerilog code

Coding standards

HDL coding standard	Select coding standard guidelines
Show passing rules in coding standard report	Include passing rules in coding standard report
Check for duplicate names	Check for duplicate names in design
Check for HDL keywords in design names	Check for HDL keywords in design names
Check module, instance, entity name length	Whether to check module, instance, and entity name length
Check signal, port, and parameter name length	Whether to check signal, port, and parameter name length
Check for clock enable signals	Whether to check for clock enable signals in generated code
Detect usage of reset signals	Whether to check for reset signals in generated code
Detect usage of asynchronous reset signals	Whether to check for asynchronous reset signals in generated code
Minimize use of variables	Whether to minimize use of variables
Check for initial statements that set RAM initial values	Whether to check for initial statements that set RAM initial values
Check for conditional statements in processes	Whether to check for length of conditional statements
Check for assignments to the same variable in multiple cascaded control regions	Whether to check if there are assignments to same variable in multiple cascaded control regions (Since R2021b)
Check if-else statement chain length	Whether to check if-else statement chain length
Check if-else statement nesting depth	Whether to check if-else statement nesting depth
Check multiplier width	Whether to check multiplier bit width
Check for non-integer constants	Whether to check for non-integer constants
Check line wrap length	Whether to check line lengths in the generated HDL code

Comments

Enable Comments	Whether to enable comments
Comment in header	Comment lines in header of generated HDL and test bench files
Emit time/date stamp in header	Include time and date information in generated HDL file header
Include requirements in block comments	Include requirements as comments in code or code generation reports
Custom File Header Comment	Custom comment in header of generated HDL code
Custom File Footer Comment	Custom comment in footer of generated HDL code

Model Generation

Generated model	Generate model that shows latency and numeric differences between model and HDL code
Validation model	Generate validation model
Suffix for validation model name	Suffix to append to validation model name
Prefix for generated model name	Prefix to append to generated model name
Layout style	Layout style of generated HDL model (Since R2021b)
Auto signal routing	Automatic routing of signals in generated model
Inter-block horizontal scaling	Horizontal scaling of generated model
Inter-block vertical scaling	Vertical scaling of generated model

Advanced

Check for name conflicts in black box interfaces	Generate warning or error when black box interfaces have name conflicts
Generate HDL code	Enable code generation for model or subsystem
Suppress out of bounds access errors by generating simulation-only index checks	Generate logic that prevents array indices from going out of bounds (Since R2022a)

Report

Generate traceability report	Generate report with hyperlinks from code to model and model to code
Traceability style	Type of traceability to generate in code generation report
Generate model Web view	Include Web view in code generation report
Generate resource utilization report	Generate resource utilization section in code generation report
Generate optimization report	Generate optimization sections in code generation report
Generate high-level timing critical path report	Insert highlighting script that maps estimated critical path in code generation report
Custom Timing Database Directory	Path to custom timing files (Since R2021b)

Test Bench

Simulation tool	Simulator to use to run generated test benches
HDL code coverage	Enable HDL code coverage flags in generated simulator scripts
HDL test bench	Enable HDL test bench generation
Cosimulation model	Generate cosimulation model
SystemVerilog DPI test bench	Enable SystemVerilog DPI test bench generation
Test bench name postfix	Suffix to append to test bench name
Force clock	Whether test bench forces clock input signals
Clock high time (ns)	Period during which test bench drives clock input signals high
Clock low time (ns)	Period during which test bench drives clock input signals low
Hold time (ns)	Hold time for input signals and forced reset input signals
Force clock enable	Whether test bench forces clock enable input signals
Clock enable delay (in clock cycles)	Elapsed time between deassertion of reset and assertion of clock enable
Force reset	Whether test bench forces reset input signals
Reset length (in clock cycles)	Length of time during which reset is asserted
Hold input data between samples	Hold data values for subrate signals for number of base-rate clock cycles in subrate sample period
Initialize test bench inputs	Specify initial value driven on test bench inputs before data is asserted to DUT
Multi-file test bench	Divide generated test bench into helper functions, data, and HDL test bench code files
Test bench data file name postfix	Suffix to append to test bench data file name when generating multi-file test bench
Test bench reference postfix	Suffix to append to names of reference signals generated in test bench code
Use file I/O to read/write test bench data	Create data files for reading and writing test bench input and output data
Ignore output data checking (number of samples)	Number of samples during which output data checking is suppressed
Floating point tolerance check based on	Check for errors in floating-point library based on relative or ULP errors
Tolerance Value	Floating-point tolerance value
Simulation library path	Path of compiled Altera or Xilinx simulation libraries

EDA Tool Scripts

Generate EDA scripts

Enable generation of third-party electronic design automation script files

Compilation Script Parameters

Compile file postfix	Postfix to append to DUT or test bench name for compilation script file name
Compile initialization	Format name to use to write `Init` section of compilation script
Compile command for VHDL	Format name to use to write `Cmd` section of compilation script for VHDL
Compile command for Verilog or SystemVerilog	Format name to use to write `Cmd` section of compilation script for Verilog or SystemVerilog
Compile termination	Format name to use to write termination section of compilation script

Simulation Script Parameters

Simulation file postfix	Postfix to append to DUT or test bench name
Simulation initialization	Format name to use to write initialization section of simulation script
Simulation command	Format name to use to write simulation command
Simulation waveform viewing command	Waveform viewing command to write to simulation script
Simulation termination	Format name to write to write termination section of simulation script
Simulator flags	Simulator flags to apply to generated compilation scripts
Choose synthesis tool	Specify synthesis tool for which to generate synthesis scripts
Synthesis file postfix	Postfix to append to file name
Synthesis initialization	Format name to use to write initialization section of synthesis script
Synthesis command	Format name to use to write synthesis command
Synthesis termination	Format name to use to write termination section of synthesis script
Additional files to add to synthesis project	Additional HDL or constraint files

Lint Script Parameters

Choose HDL lint tool	Specify HDL lint tool for which to generate lint scripts
Lint initialization	Format name to use to write initialization section of HDL lint script
Lint command	Format name to use to write command for HDL lint script
Lint termination	Format to use to write termination section of HDL lint script

Topics

Using HDL Workflow Advisor

Workflows in HDL Workflow Advisor
Learn about the HDL Workflow Advisor and various workflows you can choose and platforms you can target.
Getting Started with the HDL Workflow Advisor
Learn the basics of the HDL Workflow Advisor and how to run various tasks.
HDL Workflow Advisor Tasks
Describes HDL Workflow Advisor tasks.
Generate Code and Synthesize on FPGA Using HDL Workflow Advisor
The HDL Workflow Advisor guides you through the stages of generating HDL code for a Simulink subsystem and the FPGA design process, such as:
Generate RTL Lint Check Report Using HDL Workflow Advisor and Synopsys SpyGlass Lint Tool
Generate RTL lint check report using HDL Workflow Advisor and SpyGlass Lint tool.
Generate HDL Code and Perform Synthesis Using Cadence Genus on ASIC Devices
Generate HDL code and perform synthesis using HDL Workflow Advisor and Cadence Genus on ASIC devices.

Using Model Configuration Parameters Dialog Box

Set HDL Code Generation Options
Access HDL options in the Configuration Parameters dialog box, Simulink toolstrip, block context menu, or HDL Block Properties window.
Generate HDL Code from Simulink Model Using Configuration Parameters
Use the Configuration Parameters dialog box to generate HDL code for your Simulink model.
Obfuscate Generated HDL Code from Simulink Models
Learn how to obfuscate the generated VHDL^®, Verilog^® or SystemVerilog code from your model.

Model Configuration Parameters

Model Configuration Parameters: HDL Code Generation
Use this pane to set code generation parameters, initiate compatibility checking, and generate HDL code for your design.
Model Configuration Parameters: Target
Use this pane to specify the target hardware settings.
Model Configuration Parameters: Optimization
Use this pane to improve area and timing.
Model Configuration Parameters: Floating Point
Use this pane to specify floating-point IP libraries.
Model Configuration Parameters: Global Settings
Use this pane to specify detailed characteristics of the generated code.
Model Configuration Parameters: Report
Use this pane to specify the generation of reports.
Model Configuration Parameters: Test Bench
Use this pane to determine characteristics of generated test bench code.
Model Configuration Parameters: EDA Tool Scripts
Use this pane to control generation of script files for third-party HDL simulation and synthesis tools.