You can prototype your algorithms on FPGA-based hardware, regardless of how much FPGA design experience you have.
With MATLAB® and Simulink®, you can:
- Build a hardware-ready design using proven IP blocks and subsystems
- Simulate system-level hardware behavior to eliminate bugs before deploying to the FPGA
- Generate HDL and C code that can target any FPGA or SoC device
- Automatically deploy to Xilinx® and Intel® FPGA and SoC boards and kits
- Probe and capture signals running in hardware
“We have a wealth of experience in our domain but little experience with FPGA integration. Simulink and HDL Coder enabled us to focus on designing intelligent algorithms for our product and not on how to run those algorithms on a specific FPGA.”Boris Van Amerongen, Orolia
Using MATLAB for FPGA Prototyping
You can incrementally add live hardware elements to your design, from simulating your algorithm with live over-the-air input/output to full deployment on an FPGA or SoC software-defined radio platform or custom board.
The hardware-proven wireless design IP blocks and subsystems in Wireless HDL Toolbox™ let you get started quickly. IP includes examples that show you how to incrementally transition from algorithm design using MATLAB to wireless-system implementation models in Simulink. All of the IP has been quantized to fixed-point, and you can then use Fixed-Point Designer™ to manage quantization of the custom logic that you add before deployment with HDL Coder™.
- Hardware Design
- Software-Defined Radio using MATLAB and Simulink (34:04)
- Deploying 5G NR Wireless Communications on FPGAs: A Complete MATLAB and Simulink Workflow
- Verifying Millimeter Wave RF Electronics on a Zynq RFSoC Based Digital Baseband
- Wireless Prototyping and Production Development Essentials
- Hardware Design and Testing Solutions
- High-Speed Radar and 5G NR GSPS Processing on FPGAs and SoCs (5:38)
Motor and Power Electronics Control Applications
You can explore the performance of control algorithms running on FPGA-based hardware or accelerate plant models with FPGA-based hardware-in-the-loop. With broad HDL code generation support for math and trigonometric functions in fixed-point or native floating point, HDL Coder provides you with a straightforward path from a Simulink model to hardware.
If you are exploring how to partition your algorithm for SoC deployment, you can search and simulate partitioning strategies to assess performance before deploying to a prototype platform. Then target pre-configured kits, Speedgoat hardware, or your own custom board.
Video and Image Processing Applications
You can prototype vision algorithms on FPGA-based platforms connected to MATLAB and Simulink by automatically generating HDL and C code. Also, you can use hardware-proven vision processing blocks to build an implementation model to simulate hardware behavior such as pixel streaming, neighborhood-based algorithms, external memory access, and control signals.
Support for deploying your models to off-the-shelf FPGA evaluation kits with cameras is available. Alternatively, your hardware team can build support for your platform so you can deploy prototypes directly from MATLAB and Simulink.
Deep Learning Inference
With just a few MATLAB commands, you can accelerate deep learning inference by prototyping networks on FPGA and SoC boards. Then you can iterate on your network from within MATLAB by analyzing the performance of inferencing on the FPGA, adjusting the network, quantizing to fixed-point, and re-deploying. Finally, you can generate a target-independent HDL IP core to handoff to the hardware team for implementation.
FPGA Prototype Debugging
FPGA prototyping with real-world input helps you discover bugs that were not found and fixed with early simulation. You can insert logic into your FPGA or SoC prototype that lets you use MATLAB commands to interactively read from and write to AXI-accessible registers or to capture data from test points internal to the FPGA fabric.
If you prefer to run your FPGA prototype using your MATLAB or Simulink testbench, FPGA-in-the-loop automates the setup and manages the simulation interface to send data to the FPGA and read it back to your testbench.