Vision HDL Toolbox
Design image processing, video, and computer vision systems for FPGAs and ASICs
Vision HDL Toolbox™ provides pixel-streaming algorithms for the design and implementation of vision systems on FPGAs and ASICs. It provides a design framework that supports a diverse set of interface types, frame sizes, and frame rates. The image processing, video, and computer vision algorithms in the toolbox use an architecture appropriate for HDL implementations.
The toolbox algorithms are designed to generate readable, synthesizable code in VHDL® and Verilog® (with HDL Coder™). The generated HDL code is FPGA-proven for frame sizes up to 8k resolution and for high frame rate (HFR) video.
Toolbox capabilities are available as MATLAB® functions, System objects™, and Simulink® blocks.
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Jumpstart development of image conditioning hardware using examples of noise removal, gamma correction, and histogram implementations.
Hardware-Accelerated Vision Processing
Model and simulate efficient hardware implementations of vision processing algorithms, such as conversions, filtering, morphology, and statistics. Then use HDL Coder to generate synthesizable VHDL or Verilog RTL.
Processing Multiple Pixels Per Clock
Process 4k, 8k, or high-frame-rate video at FPGA clock rates by specifying parallel streams of 4 or 8 pixels. The underlying hardware implementation is automatically updated to support simulation and code generation with the specified parallelism.
Built-In Hardware Data Management
Use Vision HDL Toolbox blocks to automatically manage streaming input data, such as control signals, region-of-interest (ROI) windows, and line buffers. Use HDL Coder to generate VHDL or Verilog RTL for the control functionality you model and simulate.
Conversion Between Frames and Pixels
Convert full-frame video to a stream of pixels with control signals for processing in hardware. Then convert the streaming hardware output to frames for verification against your golden reference algorithm.
Prototype Platform with Live Video Input
Prototype your vision processing application by downloading the Vision HDL Toolbox Support Package for Xilinx® Zynq®-Based Hardware and using HDL Coder and Embedded Coder® to generate code from your MATLAB or Simulink implementation.
Use HDL Coder to generate high-quality, target-independent RTL and AXI interfaces from your hardware subsystem models.
Vision Processing for FPGA
Watch this five-part video series that introduces key concepts and the workflow for targeting vision applications to FPGAs for prototyping and production.