PLL Design and Verification Using Data Sheet Specifications Including Phase Noise
Use Mixed-Signal Blockset™ to model a commercial off-the-shelf integer-N Phase-Locked Loop (PLL) with dual modulus prescaler operating around 4GHz. Verify the performance of this PLL frequency synthesizer, including phase noise, lock time, and operating frequency.
Start by modeling the VCO using the phase noise profile measured in the frequency domain. Provide the charge pump programmable current, the specifications of the 3rd-order loop filter, and the parameters of dual-modulus programmable prescaler. Verify the closed- and open-loop performance of the PLL before running time-domain simulations.
Published: 6 Jun 2019
This example shows how to use Mixed-Signal Blockset to model a commercial off-the-shelf integer-N PLL with dual modulus prescaler operating around 4GHz. The goal of this demonstration is to verify the PLL performance, including phase noise.
For convenience, you start with the data sheet of a commercial device. For this example, you use the data sheet of Skyworks SKY73134-11. This is a wideband PLL Frequency Synthesizer operating between 350MHz and 6.2GHz.
First, you inspect the data sheet to identify the characteristics of the VCO. This is the main component contributing to the phase noise of the PLL. The VCO sensitivity KVCO is 20MHz/V in the typical case.
For this example, you simulate the PLL behavior when locking around 4GHz. The VCO phase noise profile around 4GHz is:
To speed up simulation, ignore the phase noise data points at lower frequency offsets. Simulation will take longer to capture the phase noise profile close to the carrier.
You first use the VCO model from Mixed-Signal Blockset. You specify the VCO sensitivity using the same value provided by the data sheet. As the free running frequency is not provided, you can set it to an arbitrary value close enough to the operating frequency. In this case, you set it to 4.2GHz.
You also specify the same phase noise profile as the one provided by the data sheet.
You connect the VCO model to a VCO testbench also from Mixed-Signal Blockset. You can autofill the measurement parameters for both the setup and the target metric. The target metric provides the anticipated phase noise profile for comparison with the simulation results. The testbench setup properties define the signal sampling frequency and the measurement resolution bandwidth.
To speed up simulation time, you reduce the sampling frequency to 4 times the lock frequency, 4*4GHz, and reduce the number of spectral averages to 4.
You run the simulation, and you can verify that the VCO model reproduces the phase noise profile specified in the target metric.
You can proceed with modeling the complete PLL system and verify its phase noise performance. From the data sheet, you see that this PLL is of type integer-N and it uses a dual modulus prescaler. The data sheet also provides the settings for the prescaler. You can therefore use an architecture model Integer-N PLL with dual modulus prescaler from Mixed-Signal Blockset.
You open the mask of the PLL block and provide the specs for each of the subsystems. For the PFD, the data sheet does not provide any detail, and therefore we leave the deadband compensation to its default value.
For the charge pump, the data sheet provides the typical value for the current of 2.7mA. You specify the same value in the PLL model.
For the VCO, you use the same specs that were verified at the previous step. The sensitivity is equal to 20MHz/V. You specify a free running frequency that is close to the final locking frequency and equal, for example, to 4.18GHz. You also include phase noise with the same profile just simulated.
For the PLL to lock at 4.2GHz when using an arbitrary reference oscillator operating at 1.6MHz, you need a divider ratio equal to:
4.2e9/1.6e6 = 2625.
For the prescaler, you use the 16/17 settings. To achieve the desired ratio, you need to use a programmable counter equal to 163:
163*16+17 = 2625
The Mixed-Signal Blockset PLL model provides the possibility to design the loop filter starting from the desired loop bandwidth, phase margin, and given filter architecture.
In this case, you manually provide the values for the filter implementation. You use the filter component values provided in the evaluation board schematic recommended in the data sheet, and manually specify the same values for the network of resistors and capacitors. These values are used to compute the loop filter transfer function.
You verify the closed- and open-loop performance of the PLL with this implementation of the loop filter. The resulting phase margin is 55 degrees. You can use this setup to design different loop filters and verify your design; for example, to use this PLL over a different operating frequency.
At last, to verify the PLL locking behavior in the time domain, you probe and plot the output signal of the loop filter.
You now connect the PLL to a Mixed-Signal Blockset PLL testbench to validate its performance.
The testbench defines the stimuli used to test the PLL. In this case we use a square waveform with 1.6MHz frequency.
You set up the testbench to measure the operating frequency, the lock time, and the phase noise.
The data sheet specifies a 1ms lock time with 1ppm frequency error; that is to say, 4.2kHz. You provide the same error tolerance.
For measuring the phase noise, we use similar configuration to the one used for the VCO, but we reduce the resolution bandwidth for higher accuracy.
For the target metric, you refer to the data sheet for both the lock time and to the closed-loop phase noise measurements performed on the evaluation board. The phase noise profile measured at 4.2GHz is:
With this setup you can run the PLL simulation and verify the performance.
In this case, the simulation takes a few minutes. We fast forward to final steps of the simulation for the benefit of this demonstration.
To speed up simulation time, you can relax the settings for measuring the phase noise; for example, using a larger resolution bandwidth or reducing the number of spectral averages.
You have used Mixed-Signal Blockset to model a PLL based on its data sheet specifications. You can use such a model, for example, to explore and design different loop filters, to use the PLL over different operating frequencies, to determine different divider ratios, or to assess the frequency synthesizer performance once embedded in a larger system. For example, Mixed-Signal Blockset PLL models can be helpful if you need to integrate a PLL into a system on chip or a system on board.
For more information, please visit the Mixed-Signal Blockset product page on mathworks.com.
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