HDL-Optimized Filters and Transforms
R2026bThese DSP HDL Toolbox™ blocks and System objects implement hardware-friendly architectures and support HDL code generation when used with HDL Coder™. These blocks and System objects have high-throughput streaming interfaces, hardware control signals, and options to select different hardware implementations of their algorithms.
You can access these hardware-optimized algorithms, with the same interface and configuration options and without creating a model or script, by using the DSP HDL IP Designer app.
Apps
| DSP HDL IP Designer | Configure and generate HDL code for digital signal processing IP cores (Since R2024b) |
Blocks
 | FFT | Compute fast Fourier transform (FFT) |
 | IFFT | Compute inverse fast Fourier transform (IFFT) |
 | Channelizer | Polyphase filter bank and fast Fourier transform |
 | Channel Synthesizer | Combine narrowband signals into multichannel signal (Since R2022a) |
 | Discrete FIR Filter | Finite-impulse response filter |
 | Biquad Filter | Biquadratic IIR (SOS) filter (Since R2022a) |
 | LMS Filter | Minimize error between observed and desired signals (Since R2023a) |
 | Farrow Rate Converter | Polynomial sample-rate converter (Since R2022a) |
 | FIR Decimator | Finite impulse response (FIR) decimation filter |
 | FIR Interpolator | Finite impulse response (FIR) interpolation filter (Since R2022a) |
 | CIC Decimator | Decimate signal using CIC filter |
 | CIC Interpolator | Interpolate signal using CIC filter (Since R2022a) |
 | FIR Rate Converter | Upsample, filter, and downsample input signal |
 | NCO | Generate real or complex sinusoidal signals |
 | Complex to Magnitude-Angle | Compute magnitude and phase angle of complex signal using CORDIC algorithm |
 | Downsampler | Downsample by removing data samples between input samples (Since R2022b) |
 | Upsampler | Upsample by adding zeros between input samples (Since R2022b) |
Objects
Topics
- High-Throughput HDL Algorithms
Choose a block that supports frame-based processing for HDL code generation.
- Hardware Control Signals
Hardware control signals such as valid and reset used by DSP HDL Toolbox blocks.
- FIR Filter Architectures for FPGAs and ASICs
Learn how DSP HDL Toolbox blocks implement hardware-friendly filter architectures.
- Generate HDL for Preconfigured Algorithm with DSP HDL IP Designer App
Load a preconfigured algorithm into the app from the command line or from the Filter Designer app.
- Control Data Rate Using Ready Signal
Implement backpressure and regulate output rate in an interpolator system.
Featured Examples
Gigasamples-per-Second Correlator and Peak Detector
Implement a high-throughput correlator and peak detector suitable for LiDAR and mm-wave RADAR applications on FPGA.
NFC Digital Downconverter
Design a high rate-change factor DDC for near-field communications systems on FPGAs.
Fractional Delay Filters
Implement fractional delay filters for hardware, including a variable fractional delay filter that uses a Farrow algorithm.
High Performance DC Blocker for FPGA
Create a DC blocking filter for a hardware communications system.
Frequency-Domain Filtering in HDL
Implement a filter in the frequency domain. The filter is built with the FFT and IFFT blocks from DSP HDL Toolbox™.
Partly Serial Systolic FIR Filter Implementation
Implement a 32-tap lowpass FIR filter that shares multiplier resources within the filter.
Fully Parallel Systolic FIR Filter Implementation
Implement a 25-tap lowpass FIR filter.
Programmable FIR Filter for FPGA
Implement a programmable FIR filter for hardware and load the filter coefficients by using a memory-style interface.
Optimize Programmable FIR Filter Resources
Implement a programmable FIR filter that optimizes multiplier resources for patterns in coefficients.
HDL Implementation of Four Channel Synthesizer and Channelizer
Synthesize four stereo signals into a broadband signal and split the signal back into the individual narrowband signals.
Align Parallel Data Streams
Align data streams with different operation latencies by using FIFO-based buffering.
Generate Sine Wave
Generate a sine wave by using the NCO block.
Implement atan2 Function for HDL
Implement the atan2 function in hardware by using the
Complex to Magnitude Angle block.
HDL Implementation of Variable-Size FFT
Implement variable-size FFT by using single FFT core.
