RAM Mapping
R2026bRAM mapping is an area optimization that maps storage and delay elements in your Simulink® model or MATLAB® code to random access memory (RAM) rather than to individual registers on hardware. RAM mapping can reduce the amount of area that your design uses in the target hardware by reducing the number of registers that elements consume and store those elements in RAM blocks.
Functions
coder.hdl.ramconfig | Specify RAM mapping configuration for persistent array variables (Since R2023b) |
Model Settings
| Map pipeline delays to RAM | Map pipeline registers in generated HDL code to RAM |
| RAM mapping threshold | Specify minimum RAM size for mapping to block RAMs |
| Map lookup tables to RAM | Map lookup tables to block RAM |
Topics
- Apply RAM Mapping to Optimize Area
Map elements to RAM to optimize area on your target hardware.
- Manage How HDL Coder Maps RAM
Learn how HDL Coder™ settings affect RAM mapping.
- RAM Mapping with the MATLAB Function Block
How to use RAM mapping optimization with
MapPersistentVarsToRAMparameter for MATLAB Function blocks in your model. - Map Persistent Arrays and dsp.Delay Objects to RAM
If your MATLAB code or Simulink MATLAB Function block contains long persistent arrays or
dsp.DelaySystem object™ objects, you can reduce the FPGA resources that your design uses by mapping them to block RAM. - Map Matrices to ROM
Map matrices to implement ROM in MATLAB and Simulink.
- Configure Custom Synthesis Attributes for Simulink Blocks
This example shows how to configure custom synthesis attributes for a Simulink model using the command-line interface and propagate them to the generated HDL code.
- Use Synthesis Attributes to Map Adders to DSPs on FPGAs
Apply synthesis attributes to map adders to dedicated DSP slices for optimized FPGA implementation. (Since R2026a)
Featured Examples
Get Started with RAM and ROM in Simulink
Configure RAM blocks in Simulink® to generate synthesizable HDL code by using HDL Coder™. The generated code can be mapped by synthesis tools to dedicated RAM resources available in FPGA devices. This example also shows how to model ROM behavior in Simulink.
Map Matrices to Block RAMs to Reduce Area
Use the RAM mapping optimization in HDL Coder™ to map persistent matrix variables to block RAMs in hardware.
