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Synthesis and Timing Analysis

Generate synthesis scripts and retrieve synthesis results

You can enable or disable the generation of compilation, simulation, or synthesis scripts by using the makehdl or makehdltb functions and then customize the names and content of the generated script files. You can also generate Tcl commands for specific synthesis tools by specifying synthesis objectives such as area optimization, compile optimization, or speed optimization in the HDL Workflow Advisor or in the HDL Workflow command line interface.


hdlsetuptoolpathSet up system environment to access FPGA synthesis software