Check clock settings

Check ID: com.mathworks.HDL.ModelChecker.runClockChecks

Check ID: com.mathworks.HDL.ModelAdvisor.runClockChecks

Check constraints on clock signals.

Available with Simulink^® and HDL Coder™.

Description

This check detects multiple constraints on clock signals that correspond to these industry-standard rules:

• Rule 1.B.A.1: Design should have only a single clock and use only one edge of the clock. This rule may be violated if you have the ClockInputs property set to Multiple.

• Rule 1.D.C.6: Do not use flip-flops with inverted edges.

• Rule 1.D.D.2: One hierarchical level should have a single clock only. This rule can be violated if you set ClockInputs to Multiple, or your design uses trigger signals and enabling TriggerAsClock can result in clock signals at various levels in the hierarchy.

Results and Recommended Actions

To fix this warning, click Modify Settings and the code generator:

• Updates the ClockInputs property to Single.

• Disables the TriggerAsClock setting.

See Also

Rules 1.B.A.1, 1.D.C.6, and 1.D.D.2 of Basic Coding Practices.