You can customize and edit HDL code generation options and then generate code at the command line. This example illustrates how you can use the Configuration Parameters dialog box to generate HDL code for the Symmetric FIR filter model.
Before you generate HDL code, the model must be compatible for HDL code
generation. To check and update your model for HDL compatibility, see Check HDL Compatibility of Simulink Model Using HDL Code Advisor. You can also
customize the model parameters by using the
This example uses the Symmetric FIR filter model that is compatible for HDL code generation. To open this model at the command line, enter:
The model uses a division of labor that is suitable for HDL design.
symmetric_fir subsystem, which implements the
filter algorithm, is the device under test (DUT). An HDL entity is
generated from this subsystem.
The top-level model components that drive the subsystem work as a test bench.
The top-level model generates 16-bit fixed-point input signals for
symmetric_fir subsystem. The Signal From Workspace block
generates a test input (stimulus) signal for the filter. The four
Constant blocks provide filter coefficients. The
Scope blocks are used for simulation and are not used for HDL
To navigate to the
Create a folder named
sl_hdlcoder_work stores a local copy of the example
model and folders and generated HDL code. Use a folder location that is
not within the MATLAB folder tree.
sl_hdlcoder_work folder your working
folder, for example:
Save a local copy of the
sfir_fixed model to your
current working folder. Leave the model open.
To generate HDL code for the DUT, you use the
makehdl function. For example, to
generate HDL code for the
To specify the customizations before you generate HDL code, use the
hdlset_param function. You can
also specify various name-value pair arguments with the
function to customize HDL code generation options while generating HDL code. For
example, to generate Verilog code, use the
makehdl('sfir_fixed/symmetric_fir', 'TargetLanguage', 'Verilog')
hdlset_param, set this parameter on the model and then run the
hdlset_param('sfir_fixed', 'TargetLanguage', 'Verilog') makehdl('sfir_fixed/symmetric_fir')
HDL Coder™ compiles the model before generating code. Depending on model display options such as port data types, the model can change in appearance after code generation. As code generation proceeds, HDL Coder displays progress messages in the MATLAB command line with:
Link to the Configuration Set that indicates the model for which the Configuration Parameters are applied.
Links to the generated files. To view the files in the MATLAB Editor, click the links.
symmetric_fir.vhd: VHDL code. This file
contains an entity definition and RTL architecture implementing
ModelSim® compilation script (vcom command) to compile the
generated VHDL code.
symmetric_fir_synplify.tcl: Synplify® synthesis script.
symmetric_fir_map.txt: This report maps
generated entities to the subsystems that generated them. See
Trace Code Using the Mapping File
The process completes with the message:
### HDL Code Generation Complete.