HDL Verifier

R2026b
Verify ASIC and FPGA designs with HDL cosimulation and generated testbenches

HDL Verifier™ enables you to reuse your system-level design environment in your HDL design and verification environment for FPGAs and ASICs. You can test and verify RTL designs against golden reference models in MATLAB® and Simulink®, debug designs using HDL simulators, and generate testbenches and verification IP.

Use HDL cosimulation to verify ASICs and FPGAs with testbenches that run in MATLAB and Simulink with RTL code that runs in your HDL simulator. You can generate SystemVerilog DPI-C models from MATLAB, Simulink, and Simscape™ to perform functional verification using digital and mixed-signal simulation in HDL simulators. You can also generate Universal Verification Methodology (UVM) components from MATLAB and Simulink for production workflows or generate SystemC™ TLM 2.0 Transaction Level Models (TLMs) from Simulink models for virtual platform simulation. All these capabilities are compatible with existing HDL code and code generated by HDL Coder™.

Get Started

Learn the basics of HDL Verifier

Algorithm Verification

Link MATLAB or Simulink to your HDL design

Export of Verification IP

Generate HDL testbench components for ASIC and advanced FPGA designs

Verification of Generated HDL Code

Generate testbenches to verify HDL code generated with HDL Coder