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Generate Individual UVM Component from Simulink

In HDL Verifier™, you can generate individual UVM components and additional required artifacts from a Simulink® subsystem for the following components:

  • UVM Sequence

  • UVM Predictor

  • UVM Scoreboard

You can generate UVM artifacts (such as sequence, predictor, or scoreboard) from an isolated Simulink model , and then embed the generated UVM artifacts in an existing UVM test environment. Alternatively, you can hand them off for continued development.

To generate a component from your Simulink model:

  1. Open the HDL Verifier app and set HDL Verifier Mode to DPI Component Generation.

  2. In the Prepare section, click SystemVerilog Settings. Then in the SystemVerilog DPI pane, set Component template type to UVM Sequence, UVM Predictor, or UVM Scoreboard. Click OK.

    Configuration Parameters open on the SystemVerilog DPI pane, and the "Component template type" menu is expanded to show UVM Sequence, UVM Predictor, and UVM Scoreboard.

  3. Select the subsystem in your model and click Generate DPI Component.

Now you can include the generated component in your UVM testbench.