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UVM Generation

Generate UVM components from Simulink® subsystems

Generate Universal Verification Methodology (UVM) test components and a behavioral design under test (DUT) from a Simulink model. You can use the generated components in two ways.

  • Generate a UVM top model with a test bench and a behavioral (DUT). Use the generated UVM top module as a test environment, and replace the generated behavioral DUT with your own simulation model.

  • Generate UVM test components, and integrate them into your existing UVM environment.

This feature requires Simulink Coder™.

Functions

uvmbuildGenerate UVM test bench from Simulink model

Objects

uvmcodegen.uvmconfigUVM configuration object

Topics

UVM Component Generation Overview

Generate a Universal Verification Methodology (UVM) from a Simulink model.

Customize Generated UVM Code

Customize file banners and HDL simulation timescale when generating a UVM test bench.

Generate SystemVerilog Assertions and Functional Coverage from verify Statement

Generate SystemVerilog DPI checks from a verify statement, and collect functional coverage information (requires Simulink Test™ license).

Use Tunable Parameters to Generalize UVM Simulation

Generate UVM parameters from Simulink tunable parameters.

Tunable Parameters in Sequence Subsystem

Generate random constraint parameters in UVM sequence from Simulink tunable parameters.

Tunable Parameters in Scoreboard Subsystem

Generate random constraint parameters in UVM scoreboard from Simulink tunable parameters.

Featured Examples