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uvmcodegen.uvmconfig

UVM configuration object

    Description

    The uvmcodegen.uvmconfig object is a universal verification methodology (UVM) configuration object. Use this object to configure UVM generation options such as the HDL simulation timescale.

    Creation

    Description

    cfgUvm = uvmcodegen.uvmconfig creates a default UVM configuration object that configures parameters for generated SystemVerilog code.

    example

    cfgUvm = uvmcodegen.uvmconfig(Name,Value) sets properties using one or more name-value pair arguments. Enclose each property name in quotes. For example, uvmcodegen.uvmConfig('timescale','1ps/1ps') specifies a UVM configuration object with a timescale signature of one picosecond for the time unit and one picosecond for the HDL simulation precision.

    Properties

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    HDL simulator timescale directive, specified as 'Tu/Tp', where Tu is the time unit, and Tp is the time precision.

    Example: 10us/100ns specifies a time unit of ten microseconds with an HDL simulation precision of one hundred nanoseconds.

    Data Types: char | string

    Examples

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    Configure the generated UVM test bench to a timescale of 1ns/1ps. In this case, the time unit is one nanosecond, with simulation precision of one picosecond.

    cfgUVM=uvmcodegen.uvmconfig('timescale','1ns/1ps')
    cfgUVM = 
      uvmconfig with properties:
    
        timescale: '1ns/1ps'
    
    
    Introduced in R2020b