Generate UVM test bench from Simulink model
generates a SystemVerilog top module, which includes a Universal Verification Methodology
(UVM) test bench and a behavioral design under test (DUT). The UVM test bench includes a
sequence, a scoreboard, monitors, and drivers. The
The Simulink® DUT subsystem to a generated SystemVerilog DPI behavioral DUT
The Simulink sequence subsystem to a UVM sequence block
The Simulink scoreboard subsystem to a UVM scoreboard
uvmbuild(___, ) specifies options
using one or more name-value pair arguments in addition to the input arguments in the
previous syntax. For example,
a UVM driver from the Simulink subsystem specified as
Simulink Model Structure
This example uses a Simulink® model, that includes these three subsystems.
A sequence subsystem, which generates stimulus for the DUT.
A DUT subsystem, which represents your HDL design.
A scoreboard subsystem, which collects the outputs and checks them. In this example the DUT is a simple delay block.
Generate UVM Test Bench
Generate a UVM test bench from this Simulink model, specifying the paths to the DUT, sequence, and scoreboard subsystems.
Observe Generated Output
uvmbuild function creates a directory named
hdlv_uvmbuild_uvmbuild containing the
uvm_testbench directory. The
uvm_testbench directory includes these subdirectories.
top directory includes a SystemVerilog top module and generated scripts to execute in your HDL simulation environment.
DPI_dut directory contains the SystemVerilog-DPI behavioral DUT.
sequence directory contains the generated sequence transaction type and a UVM sequencer, which drives the transaction to the DUT.
scoreboard directory contains the generated UVM scoreboard.
uvm_artifacts directory contains UVM components, such as monitors, drivers, and agents, required for the UVM environment.
Run Generated UVM Test Bench
Start Modelsim® or Questasim in GUI mode.
In the HDL simulator, navigate to the top directory:
In the HDL simulator, enter this command to run your simulation:
dut— Design under test subsystem
Design under test subsystem, specified as a character vector or string scalar representing a DUT-subsystem name or full block path.
sequence— Sequence subsystem
Sequence subsystem, specified as a character vector or string scalar representing a sequence-subsystem name or full block path.
scoreboard— Scoreboard subsystem
Scoreboard subsystem, specified as a character vector or string scalar representing a scoreboard-subsystem name or full block path.
comma-separated pairs of
the argument name and
Value is the corresponding value.
Name must appear inside quotes. You can specify several name and value
pair arguments in any order as
'Driver'— Driver subsystem
Driver subsystem, specified as a character vector or string scalar representing a
driver-subsystem name or full block path. By default, the
uvmbuild function generates a passthrough UVM driver.
'Monitor'— Monitor subsystem
Monitor subsystem, specified as a character vector or string scalar representing a
monitor-subsystem name or full block path. By default, the
uvmbuild function generates a passthrough UVM monitor.
'Config'— UVM configuration parameters
UVM configuration parameters, specified as the comma-separated pair consisting of
'Config' and a
uvmcodegen.uvmconfig configuration object. Use this value to configure the
generated UVM test bench.