Use Tunable Parameters to Generalize UVM Simulation

Universal Verification Methodology (UVM) supports tunable parameters in generated SystemVerilog components in several ways.

• Create a SystemVerilog parameter using the DPI component tunable parameter methodology. For more information about using tunable parameters in DPI components, see Tune Gain Parameter During Simulation.

• Parameterize a sequence subsystem to create constrained random stimulus. For more information about tunable parameters in a sequence subsystem, see Tunable Parameters in Sequence Subsystem.

• Generalize the scoreboard for different scenario checks without the need to regenerate the UVM files. For more information about tunable parameters in a scoreboard subsystem, see Tunable Parameters in Scoreboard Subsystem.

To learn more about UVM component generation, see UVM Component Generation Overview.