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Histogram Equalization with Zynq-Based Hardware

This example shows how to target histogram equalization algorithm to the Zynq® hardware using the SoC Blockset™ Support Package for Xilinx® Devices.

This example uses a fixed reference design and the IP core generation workflow. For an example of the same algorithm implemented and deployed by using the SoC Builder workflow, see Histogram Equalization Using Video Frame Buffer. For information about these workflows, see SoC Generation Workflows.

Setup Prerequisites

This example follows the algorithm development workflow that is detailed in the Developing Vision Algorithms for Zynq-Based Hardware example. If you have not already done so, please work through that example to gain a better understanding of the required workflow.

This algorithm is based on the Vision HDL Toolbox™ example, Histogram Equalization (Vision HDL Toolbox). With the SoC Blockset Support Package for Xilinx Devices, you get a hardware reference design that allows for easy integration of your targeted algorithm in the context of vision system.

If you have not yet done so, run through the guided setup wizard portion of the Zynq support package installation. You might have already completed this step when you installed this support package.

On the MATLAB Home tab, in the Environment section of the Toolstrip, click Add-Ons > Manage Add-Ons. Locate SoC Blockset Support Package for Xilinx Devices, and click Setup.

The guided setup wizard performs a number of initial setup steps, and confirms that the target can boot and that the host and target can communicate.

For more information, see Set Up Xilinx Devices.

Pixel-Stream Model

This model provides a pixel-stream implementation of the algorithm for targeting HDL. Instead of working on full images, the HDL-ready algorithm works on a pixel-streaming interface.This model uses a YCbCr 4:2:2 Resize block that allows the source video frame to be resized for better simulation performance.Alternatively, you may want to perform a crop of the video frame. The blocks in the shaded areas convert to and from pixel stream signals in preparation for targeting.

The algorithm in this example performs histogram equalization to enhance the contrast of a video stream.The histogram of an entire video frame is computed and accumulated. The design applies equalization to the same frame for which the histogram is calculated.A frame buffer stores the input frame while the histogram is computed. When the accumulated histogram has been computed, a trigger signal releases the stored frame from the frame buffer.


Video Source The source video for this example comes from either the From Multimedia File block, that reads video data from a multimedia file, or from the Video Capture HDMI block, that captures live video frames from an HDMI source connected to the Zynq-based hardware. To configure the source, right-click on the variant selection icon in the lower-left corner of the Image Source block, choose Label mode active choice, and select either File or HW.

For this algorithm, the model is configured as listed:

  • A pixel format of YCbCr 4:2:2. This algorithm is written to work on a YCbCr 4:2:2 pixel format, and both the From Multimedia File and Video Capture HDMI blocks are configured to deliver video frames in this format. Other supported pixel formats are RGB, and Y only.

Algorithm Configuration The algorithm, in addition to processing the image for histogram equalization has some control as well.

  • pbBypass connects to a push button on the board to display the original image, without histogram equalization applied.

The pbBypass control port is a pure hardware connection in the targeted design. This port can run at any desired rate including at the pixel clock rate.

  • LED is connected to a LED on the board, and is configured to toggle periodically to indicate that the bitstream has been loaded correctly.

  • errorLED is connected to a LED on the board, and will toggle on if an unsupported video resolution is being provided at the input to the Histogram Equalization algorithm. For a list of supported video resolutions, see the Frame Size parameter of the Video Capture HDMI.

The model features a Video Frame Buffer block that provides a simplified simulation model of a frame buffer implemented in external memory. The Video Frame Buffer block is configured for a pixel format of YCbCr 4:2:2, and a video resolution of 320x240p. In the targeted design, the frame buffer connections will interface with the external memory on the chosen Zynq platform.

The Video Frame Buffer block input interface features the video pixel ports {Y, CbCr}, corresponding pixel control bus port {pixelCtrl}, and a frame buffer trigger {pop} port. The video stream that is to be stored in the frame buffer, and the corresponding video timing signals, are provided on the pixel and control bus ports. The frame buffer pop port is used to schedule the release of the stored video frame from the frame buffer. The release of the frame from the frame buffer is controlled from within the Histogram Equalization Algorithm subsystem, and should be asserted high for a single clock cycle. Once triggered, the frame buffer will release the stored frame on the video pixel output ports {Y, CbCr} with corresponding video timing signals on the pixel control bus port {pixelCtrl}.

NOTE: During the first frame of simulation output, the Video Display scope display a green image. This condition indicates that no image data is available. This behavior is because the output of the pixel-streaming algorithm must be buffered to form a full-frame before being displayed.

You can optionally run this simulation without hardware. To modify the frame size for simulation performance, change the Frame size value in the YCbCr 4:2:2 Resize, Frame To Pixels for YCbCr 4:2:2, Pixels To Frame for YCbCr 4:2:2 blocks, and Frame Buffer blocks. The lower the frame size, the faster the simulation will run. The minimum frame size is 240p.

Target the Algorithm

After you are satisfied with the pixel streaming algorithm simulation, you can target the pixel algorithm to the FPGA on the Zynq board.

Start the targeting workflow by right clicking the Histogram Equalization Algorithm subsystem and selecting HDL Code > HDL Workflow Advisor.

  • In Step 1.1, select IP Core Generation workflow and select your target platform from the list.

  • In Step 1.2, select YCbCr 4:2:2 reference design to match the pixel format of the Histogram Equalization Algorithm subsystem. Set Source Video Resolution to 1080p HDTV.

NOTE: If targeting the ZedBoard or ZC702, this model may fail to meet the applied timing constraints for a resolution of 1080p HDTV. If using ZedBoard or ZC702, set Source Video Resolution to 720p HDTV.

  • In Step 1.3, map the target platform interfaces to the input and output ports of your design. As this example uses the frame buffer interface, the relevant ports of the Histogram Equalization Algorithm subsystem must be mapped accordingly.

The video stream from the algorithm subsystem to the frame buffer is mapped to the Frame Buffer Master interface, and the video stream from the frame buffer to the algorithm subsystem is mapped to the Frame Buffer Slave interface. The frame buffer pop signal is also be mapped as part of the Frame Buffer Master interface.

With reference to Target platform interface table, map the YFromFrameBuf port to the Frame Buffer Slave interface, and select Y from the dropdown menu in the Bit Range / Address / FPGA Pin column. Similarly, select Frame Buffer Slave as the interface for the CbCrFromFrameBuf and ctrlFromFrameBuf ports, and CbCr and Pixel Control Bus from the Bit Range / Address / FPGA Pin column respectively.

Map the YToFrameBuf, CbCrToFrameBuf, ctrlToFrameBuf, and popFrame ports to the Frame Buffer Master interface, and select Y, CbCr, Pixel Control Bus, and Frame Trigger from the dropdown menu in the Bit Range / Address / FPGA Pin column respectively.

Additionally, map the pbBypass port to push button 0, and the err and LED ports to LEDs 0 and 1.

  • Step 2 prepares the design for generation by doing some design checks.

  • Step 3 generates HDL code for the IP core.

  • Step 4 integrates the newly generated IP core into the larger Vision Zynq reference design.

Execute each step in sequence to experience the full workflow, or, if you are already familiar with preparation and HDL code generation phases, right-click Step 4.1 in the table of contents on the left hand side and select Run to selected task.

  • In Step 4.2, the workflow generates a targeted hardware interface model and, if the Embedded Coder® Support Package for Xilinx® Zynq Platform has been installed, a Zynq software interface model. Click Run this task button with the default settings.

Steps 4.3 and 4.4

The rest of the workflow generates a bitstream for the FPGA, downloads it to the target, and reboots the board.

Because this process can take 20-40 minutes, you can choose to bypass this step by using a pre-generated bitstream for this example that ships with product and was placed on the SDCard during setup.

Note: For ZC706, ZCU102 and PicoZed boards, this bitstream was generated with the HDMI pixel clock constrained to 148.5 MHz for a maximum resolution of 1080p HDTV at 60 frames-per-second. For ZedBoard and ZC702 boards, this bitstream was generated with the HDMI pixel clock constrained to 74.25 MHz for a maximum resolution of 720p HDTV at 60 frames-per-second. To run this example on Zynq hardware with a higher resolution, select the Source Video Resolution value from the drop-down list in Step 1.2.

To use this pre-generated bitstream execute the following:

>> vz = visionzynq();
>> changeFPGAImage(vz, 'visionzynq-zedboard-hdmicam-histogram_equalization.bit');

To use a bitstream for another platform, replace 'zedboard' with the platform name.

Alternatively, you can continue with Steps 4.3 and 4.4.

Using the Generated Models from the HDL Workflow Advisor

Step 4.2 generated two, or four, models depending on whether Embedded Coder® is installed: A 'targeted hardware interface' model and associated library model, and a 'software interface' model and associated library model. The 'targeted hardware interface' model can be used to control the reference design from the Simulink model without Embedded Coder. The 'software interface' model supports full software targeting to the Zynq when Embedded Coder and the Embedded Coder Support Package for Xilinx Zynq Platform are installed, enabling External mode simulation, Processor-in-the-loop, and full deployment.

The library models are created so that any changes to the hardware generation model are propagated to any custom targeted hardware simulation or software interface models that exist.

Targeted Hardware Interface Model: In this model, you can adjust the configuration of the reference design and read or drive control ports of the hardware user logic. These configuration changes affect the design while it is running on the target. You can also display captured video from the target device.

Software Interface Model: In this model, you can run in External mode to control the configuration of the reference design, and read or drive any control ports of the hardware user logic that you connected to AXI-Lite registers. These configuration changes affect the design while it is running on the target. You can use this model to fully deploy a software design. (This model is generated only if Embedded Coder and the Embedded Coder Support Package for Xilinx Zynq Platform are installed.)