System Peripherals

Configure and use system peripherals such as CLA, GPIO, and Watchdog

Create Simulink^® models with the system peripherals such as CLA, GPIO, and watchdog available on TI’s C2000™ microcontrollers. Configure the Simulink model to interface with supported target hardware using model configuration parameters. You can map tasks and peripherals in a model to hardware board configurations using Hardware Mapping tool. The blocks are processor specific and is not available on all TI’s C2000 microcontrollers.

Blocks

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GPIO

C281x GPIO Digital Input	General-purpose I/O pins for digital input
C281x GPIO Digital Output	General-purpose I/O pins for digital output
F28M35x/F28M36x GPIO Digital Input	Read the logical value of a GPIO pin configured as input
F28M35x/F28M36x GPIO Digital Output	Set the logical value of a GPIO pin configured as output
C280x/C2802x/C2803x/C2805x/C2806x/C2833x/C2834x/F28M3x/F2807x/F2837xD/F2837xS/F2838x/F2838x-M4/F2800xx GPIO Digital Input	Configure general-purpose input/output pins as digital input
C280x/C2802x/C2803x/C2805x/C2806x/C2833x/C2834x/F28M3x/F2807x/F2837xD/F2837xS/F2838x/F2838x-M4/F2800xx GPIO Digital Output	Configure general-purpose input/output pins as digital input

CLA, Watchdog, Timer

C28x CLA Task	Create CLA task that executes downstream function-call subsystem on CLA core
CLA Subsystem	Group blocks to execute algorithm inside CLA (Since R2021b)
CLA Task Manager	Create and manage task executions in Control Law Accelerator (CLA) model (Since R2022a)
CLA Math	Implements CLA Math functions from CLA Math library (Since R2023a)
C28x Software Interrupt Trigger	Generate software-triggered nonmaskable interrupt
Software Trigger CPU<->CLA	Trigger software events between processor (CPU) and control law accelerator (CLA) (Since R2022a)
C28x Watchdog	Configure counter reset source of processor watchdog module
C281x Timer	Configure general-purpose timer in Event Manager module

Tools

Hardware Mapping

Map tasks and peripherals in a model to hardware board configurations (Since R2022b)

Model Settings

Model Configuration Parameters for Texas Instruments C2000 Processors

Model Configuration Parameters for Texas Instruments F2838x (ARM Cortex-M4)

Model Configuration Parameters for Texas Instruments Concerto F28M3x (ARM Cortex-M3)

Topics

Modeling and Code Generation Using Control Law Accelerator (CLA)
Use the control law accelerator (CLA) co-processor to model and generate code in C2000 MCU models.
Overview of CLA Configuration for C2000 Processors Using Subsystem
Overview of CLA Task and Subsystem, data exchange, interrupt generation and model configuration for CLA.
Modeling Control Law Accelerator (CLA) Using Model Reference
Use the control law accelerator (CLA) co-processor in C2000™ MCU models.

Featured Examples

Modify Duty Cycle of ePWM Using DMA

Configure the direct memory access (DMA) parameters to modify the ePWM duty cycle. Using DMA, the sine wave data is copied from a look-up table to the ePWM compare register.

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Using the Control Law Accelerator (CLA)

Use the Control Law Accelerator (CLA) available on some of the TI® processors using C2000™ Microcontroller Blockset.

Open Model

Getting Started with Texas Instruments C2000 Microcontroller Blockset

Use C2000™ Microcontroller Blockset to run a Simulink® model on Texas Instruments C2000 hardware.

Open Model

Control Law Accelerator in DC-DC Power Conversion Using C2000

Manage the voltage mode control (VMC) algorithm for a closed loop DC-DC power conversion system by using the Control Law Accelerator (CLA). An auxiliary software current protection loop is managed by C2000 CPU. In the TMS320F28379D and similar processor families, the CLAs execute the hard-realtime portions of the algorithm can connect with hardware perhipherals such as ADC's and PWM's. The C2000 CPU is better suited for hard real-time portions of the algorithm that require multitasking, handling of asynchronous events, and communication with other cores. While this example extends the DC-DC buck converter developed in the DC-DC Buck Converter on MCU example, the strategy presented can be applied to any design where a resource intensive hard real-time process executes on the CLA and real-time multi-tasking processes run on C2000 CPU.

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