I recall a way in Verilog to test a char read in from a file (like a buffer, I believe) and then based on what that char is, proceed in a certain way.
My current file reading uses fscanf and reads in only numbers, but the users here sometimes user True/False for a line, and sometimes 0/1. An example of a line could be either:
Fruit Bananas True Potatoes False
~~ or ~~
Fruit Bananas 1 Potatoes 0
I'm trying to migrate toward 0/1, since I don't think Matlab recognizes True/False like python can. So I want to be able to read in either file type. If the scan returns a number (after the fruit type), then I proceed with numbers, if it returns a char or string, then I proceed for that. Does anyone have suggestions? Thanks!
EDIT: My actual input file looks more like this: (a mixture)