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Difference in the output of CIC decimator while using with unbuffer and without unbuffer

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I am using a CIC decimator block to downsample a high sample rate signal . the CIC decimator output is quite diffrent when i use it without unbuffer. but as for the FPGA apllication i need to unbuffer data the output is changed what could be the possible reason for this ? and how it could be resolved

Answers (1)

Bharath Venkataraman
Bharath Venkataraman on 13 Jun 2022
Edited: Bharath Venkataraman on 13 Jun 2022
Could you please provide a model that shows this behavior (you may want to try it using a fixed known input first)?
Are you sending in the input as a Mx1 array (sending it in as a 1xN array will have the block interpret it as multi-channel data).
Bharath Venkataraman
Bharath Venkataraman on 14 Jun 2022
I want to make sure I have the problem understood correctly.
  1. You have a Simulink model with the CIC Decimator that simulates correctly.
  2. You generated HDL code and put it on the FPGA.
  3. On the FPGA, you are finding discrepancies.
If the above is true, please try using the FPGA in the Loop workflow. This will run the HDL code on the FPGA but get data in and out of Simulink. It is a good way to verify that the HDL code runs on the FPGA correctly.
On the FPGA, you can also use FPGA data capture to capture data going in and out of the filter.

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