- In Xilinx Vivado, generate a testbench for the IP core. This testbench should include the necessary stimuli and any additional logic required to interact with the IP core.
- Now, export the testbench generated in Vivado as VHDL or Verilog files.
About Xilinx Vivado ip core, How do I verify ip cores using FPGA-in-the-loop.
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I used Xilinx Vivado ip core in my project, now I would like to verify this project using the simulink. But in the FPGA-in-the-Loop Wizard Sources Files windows, I only add .v or .vhdl sources files. How to solve it? Please
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Accepted Answer
Tushar Sharma
on 27 Nov 2023
Hi,
I understand that you want to verify your project using Simulink, but you are unable to add the source files in the "FPGA-in-the-Loop Wizard" window as it only accepts VHDL or Verilog files.
To interface Xilinx Vivado IP cores with Simulink for verification, you can follow these steps:
These exported files can now be used for verification as sources for simulation in Simulink.
Hope it helps!
Best regards,
Tushar Sharma
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