HDL Verifier, FPGA in the Loop Not detecting Hardware version Information

Hi All,

I am using Simulink to create a simple Project of Half Adder using MATLAB and Simulink and try to test it with FPGA in the Loop,

But I am Facing Some Problem Like System is not able to get the harware version Information. I am using DigiLents BASYS3 FPGA Board based on Artrix7, From Board manager i have setup the complete board even at that time i was not able to verify the board but generation of programming and uploading the program was working but this version information part error is there,

Please Someone Help as i am trying to solve this problem since a very long time,

MATLAb version 2023b

VIVADO version 2022.1 and 2023.1

Answer 1

[Sachin Lodhi]

Please check if your FPGA board is in the list of supported boards for HDL Verifier( https://in.mathworks.com/help/releases/R2023a/hdlverifier/xilinxfpgaboards/ug/xilinx-fpga-board-support-from-hdl-verifier.html). I recommend you use the HDL Workflow Advisor to generate code and run FIL if your board is already supported by HDL Verifier. But if it is not supported, then the workaround would be to treat your board as a customized board and go through the process of registering that board and manually setting it up to support ethernet for FPGA-in-the-loop. For reference, you can check the below documentation link: https://in.mathworks.com/help/hdlcoder/ug/what-is-fpga-board-customization.html