How to connect a zybo Z7 20 to the Simulink using FPGA in the loop

Hi,

I want to set up FPGA-in-the-loop using my ZYBO Z7-20. I created a custom board using the FIL Wizard, but I only found the JTAG interface available. I need high-speed communication between Simulink and my ZYBO, as the sampling time is 1 microsecond. I think the JTAG interface might not be able to handle this speed, so I considered using Ethernet communication. However, when I tried to add the custom board, as you can see here...

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I couldn't find the Ethernet interface.

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So, what should I do now? Is there any other solution for my specific problem, or is it possible to make it work just using the JTAG? I tried this method, and I was able to run the FPGA-in-the-loop, but the system didn't respond as expected, meaning I got incorrect results.

I'm using Vivado 2022.1 with MATLAB 2023a.

This is the XML file for my specific custom board.

Answer 1

[BA]

• The ZYBO Zynq 7000 development board Hardware Support Package only supports JTAG interface for FIL as you have found out. You can see this in the documentation page: https://www.mathworks.com/help/hdlverifier/gs/supported-eda-tools.html?s_tid=srchtitle_site_search_1_eda%20supported#bt16i4l-9

Scroll down in the page above in the table under the title: Supported FPGA Devices for FPGA Verification

• Regarding the incorrect result in the FIL simulation, I was wondering if the data types setting under the mask of the FIL block in your model matches the data type setting you are expecting in Simulink?

• I don't think the speed of 1 micro second would be an issue for FIL in this case, since FIL mode controls what goes into DUT and receives the output.

• Another reason that your FIL simulation in JTAG is not behaving as you are expecting it, could be because of this: https://adaptivesupport.amd.com/s/article/000034528?language=en_US

Are you using multipliers in your model that could be having the issue explained in this AMD page?

I was wondering if you could make a simple model that does not have multipliers to verify the FIL behavior in general. If the problem mentioned in the link above is the problem, then the solution would be to try a later version of vivado that does not have this issue and in HDL Workflow Advisor check the option that allows you to use your version of Vivado as opposed the version we support/expect.

Please let me know if any of the above was helpful.

Thanks.