Error using spiceBase/​getConnect​ionString

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Hi.
When trying to transfer a Pspice model to Simulink, the following error appears. Can someone help me, please?
"Error using spiceBase/getConnectionString All external nodes must be connected in XCGD."
Thi is my Pspice file:
********************************************************************************
* UnitedSiC G3 650V-6.7mohm SiC Cascode Spice Circuit Model v3.1
* Copyright 2019 United Silicon Carbide, Inc.
* This is a PRELIMINARY Spice Model of UF3SC065007K4S
*
*
* The model does not include all possible conditions and effects,
* in particular it doesn't include:
* Self heating
* leakage current in blocking state
* Drain to source breakdown is notional only
*
********************************************************************************
*** UF3SC065007K4S ***
UF3SC065007K4S.CIR
*
.subckt UF3SC065007K4S nd ng ns nss
Ld nd nd1 5n
Lmd ns1 nd2 1p
Ljg ng1 ns3 5n
Lmg ng ng2 10n
Lms ns2 ns3 2n
Ls ns3 ns 2n
xj1 nd1 ng1 ns1 jfet_G3_650V_Ron params: Ron=5.0m Rg=0.5
xm1 nd2 ng2 ns2 mfet201a
Cgd nd1 ns3 7p
Rss ns2 nss 1u
.ends
*** 650V JFETs ***
.subckt jfet_G3_650V_Ron d g s params: Ron=0 Rg=0
*#ASSOC Category="N-Channel JFET" Symbol=njfet
.param Ron1={Ron}
.param Rg1={Rg}
.param a= {75m/(Ron1)}
X1 di gi s jfet_G3_650V params: ascale=(a)
XCgs gi s Cgs_650V params: acgs=(a)
XCgd gi di Cgd_650V params: acgd=(a)
Cgdex gi di {25p * (a) }
Cgsex gi s {80p * (a) }
Rd d di Rtemp {50m/(a)}
.MODEL Rtemp RES (TC1=2.112e-3, TC2=3.6244e-5)
Rgate g gi {Rg1}
.ends jfet_G3_650V_Ron
*** Shared Subcircuit for 650V JFETs ***
.subckt jfet_G3_650V d g s Params: ascale=0
.param Fc1=0.5
.param Pb1=3.25
.param M1=0.5
.param Vd0=400
.param gos={0.0178*(ascale)}
.param gfs={23.5*(ascale)}
.param f=1.763
.param vth=-10
.param cgs1=0.375n
.param cgd1=0.0404n
.param bt={((f)*(gfs9+2*(gos)*(Vd0)/(vth))/2/(-(vth))}
.param lamd={1*(gos)/(bt)/(vth9/(vth)}
.param cgs0={pwr((1+30/(Pb1)),(M1))*(cgs1)}
.param cgd0={pwr((1+(Vd0)/(Pb1)),(M1))*(cgd1)}
J1 d g s jfet_650
Dgs g s Dgs_iv
Dgd g d Dgd_iv
Rgs g s 1Meg
Rgd g d 10Meg
.MODEL jfet_650 NJF(
+ Beta=(bt) BetaTce=0 Vto=(vth) VtoTc=0 lambda=(lamd)
+ Is=1e-60
+ Cgs=((cgs0)*(ascale)) Cgd=((cgd0)*(ascale)) Fc=(Fc1) Pb=(Pb1)
+ M=(M1))
.MODEL Dgs_iv D (CJO=0 BV=40 IS=1e-50 ISR=1e-50 Eg=3.5 Rs=0)
.MODEL Dgd_iv D (CJO=0 BV=850 IBV=1m IS=1e-50 ISR=1e-50 Eg=3.5 Rs={15.1m/(ascale)})
.ends jfet_G3_650V
* Cgs network
.subckt Cgs_650V g s params: acgs=0
.param c0=1n
.param vsgmin=-2
.param vsgmax=15
.param a1={0.25n*(acgs)}
.param b1=1
.func Qgs1(u) {- (a1) / (b1) *(exp(- (b1) *u)-1)}
.param a2={0.35n*(acgs)}
.param b2=0.5
.param c2=8.7
.func Qgs2(u)
+ {if(abs(u)<{vsgmax},
+ {a2}*u + {a2}*(-{b2})*log(cosh((u-{c2})/-{b2}))
+ -{a2}*(-{b2})*log(cosh(-{c2}/-{b2})),
+ {a2}*{vsgmax} + {a2}*(-{b2})*log(cosh(({vsgmax}-{c2})/-{b2}))
+ -{a2}*(-{b2})*log(cosh(-{c2}/-{b2})))}
E1 s m1 value={v(s,g)-Qgs1(v(s,g))/(c0)}
C01 m1 g {c0}
E2 s m2 value={v(s,g)-Qgs2(limit(v(s,g),-(vsgmax),(vsgmax)))/(c0)}
C02 m2 g {c0}
.ends Cgs_650V
* Cgd network
.subckt Cgd_650V g d params:acgd=0
.param c0=1n
.param a1={0.2n*(acgd)}
.param b1=0.6
.param c1=19
.param vdgmax1=30
.func Qgd1(u)
+ {if(abs(u)<(vdgmax1),
+ (a1)*u + (a1)*(-(b1))*log(cosh((u-(c1))/-(b1)))
+ -(a1)*(-(b1))*log(cosh(-(c1)/-(b1))),
+ (a1)*(vdgmax1) + (a1)*(-(b1))*log(cosh(((vdgmax1)-(c1))/-(b1)))
+ -(a1)*(-(b1))*log(cosh(-(c1)/-{b1})))}
.param a2={0*(acgd)}
.param b2=0.5
.param c2=9.5
.param vdgmax2=15
.func Qgd2(u)
+ {if(abs(u)<{vdgmax2},
+ (-1)*({a2}*u + {a2}*(-{b2})*log(cosh((u-{c2})/-{b2}))
+ -{a2}*(-{b2})*log(cosh(-{c2}/-{b2}))),
+ (-1)*({a2}*{vdgmax2} + {a2}*(-{b2})*log(cosh(({vdgmax2}-{c2})/-{b2}))
+ -{a2}*(-{b2})*log(cosh(-{c2}/-{b2}))))}
E1 d m1 value={v(d,g)-Qgd1(limit(v(d,g),-(vdgmax1),+(vdgmax1)))/(c0)}
C01 m1 g (c0)
E2 d m2 value={v(d,g)-Qgd2(limit(v(d,g),-(vdgmax2),+(vdgmax2)))/(c0)}
C02 m2 g (c0)
.ends Cgd_650V
*** Si MOS Model ***
.SUBCKT mfet201a 4 1 2
*Gate-->1 Drain-->4 Src-->2
.param Ascale= 8.055
***Ascale used to scale the active area of the mosfet.It could be any positive data
M1 3 5 9 9 NMOS W={ (Ascale)* 2 } L= 0.00000033
M2 9 5 9 3 PMOS W={ (Ascale)* 1.5 } L= 0.00000036
Ld 4 7 0.1p
Ls 9 2 0.1p
Lg 1 8 0.1p
R1 7 3 RTEMP { 0.007 / (Ascale) }
RG 8 5 0.7
CGS 5 9 { 5.6e-10 * (Ascale) }
DBD 9 3 DBD
**************************************************************************************************************
.MODEL NMOS NMOS (LEVEL = 3
+ TOX = 6.00E-08
+ NSUB = 3.8E+17
+ VTO= 5.5
+ THETA = 0
+ kp= 1.788E-05
+ TPG = 1 )
**************************************************************************************************************
.MODEL PMOS PMOS (LEVEL = 3
+ TOX = 6.00E-08
+ NSUB = 4.8E+16
+ TPG = -1 )
**************************************************************************************************************
.MODEL DBD D (CJO={ (Ascale) * 2.6E-10 }
+ VJ= 0.7
+ M= 0.5
+ RS= {0.007/ (Ascale) }
+ IS= { (AScale) * 1.706E-12 }
+ TT= 8.00E-09
+ BV= 35
+ IBV= 0.00025 )
**************************************************************************************************************
.MODEL RTEMP RES (TC1=3E-3)
.ENDS
*** End of File ***
Thanks!

Accepted Answer

Sumukh
Sumukh on 30 Oct 2024
Moved: Sabin on 29 Nov 2024
Hi Ignacio,
I believe the error is caused by the PSpice file itself. Based on the error message, the .subckt definition at line 38 for XCgd needs to be corrected. You can refer to the following documentation to debug the issue in the netlist file:
According to the above documentation, the conversion assistant does not check for proper PSpice syntax. The netlist must be written in Cadence®PSpice format and be syntactically correct. You can refer to Cadence®PSpice resources for debugging the issue as well.
You can also refer to the following MATLAB Answers where the same issue has been found and resolved after correcting the syntax in the file:
The netlist file provided is for a FET device. Another possible workaround is to use SPICE-compatible blocks for constructing the FET SPICE model directly in Simulink. You can refer to the following documentation to know more about these blocks
The SPICE NJFET, SPICE PJFET, SPICE NMOS and SPICE PMOS blocks in the above documentation can be used to model the FET described in the netlist.

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