Assignment of elements of vector inside for-loop with conditional logics

Hi there,

I need to implement in Simulink the following logic illustrated as a simplified pseudo code below. The idea is need to update a vector based on condition inside a for-loop. Some condition may be not perform any operation on the vector elements at all.

Vector = [0, 0, 0];
For iteration=1:3
    If iteration<=1
        Vector(1) = 1;
    elseif iteration<=2
        Vector(2) = 3;
    else
    end
end

I am trying to avoid a memory block to use the whole vector from previous iteration to current iteration because of the computation effort needed to copy the whole vector. The way assignment block works within a for-loop serves this purpose well as desribed here https://www.mathworks.com/help/simulink/slref/iterated-assignment-with-assignment-block.html. However, because of the conditional logic, I am not sure if it is possible.

Appreciate for any suggestions on the implementation

Answer 1

[Umar]

Hi @John,

You have a specific condition-based logic that needs to update elements of a vector (Vector = [0, 0, 0]) during each iteration of a loop. The conditions dictate that only certain elements of the vector should be updated based on the current iteration index. The goal is to avoid copying the entire vector for every iteration, which can be computationally expensive. Here are the implementation steps listed below.

1. Set Up the Model: - Open Simulink and create a new model. - Add a For Iterator Subsystem from the Simulink library.

2. Initialize the Vector: - Within the For Iterator Subsystem, initialize your vector using a Constant block or an Inport block with values [0, 0, 0]. This will serve as your initial vector state.

3. Add an Assignment Block: - Drag an Assignment block into your For Iterator Subsystem. This block will allow you to update specific elements of the vector based on the iteration index. - Configure this block to accept two inputs: one for the vector and another for the new value to be assigned.

4. Configure Loop Logic: - Use a Switch block or Multiport Switch block to implement your conditional logic: - Connect the output of the For Iterator to control which element of the vector is updated based on the current iteration. - For iteration <= 1, connect it to update Vector(1). - For iteration <= 2,connect it to update Vector(2). - If none of these conditions are met (i.e., for iteration > 2), simply pass through the current value of that element without making any updates.

5. Connect Outputs: - Ensure that after each update, you connect the output of your Assignment block back into itself or use it as an input for subsequent iterations, allowing it to carry forward any changes made during previous iterations.

6. Final Output: - After exiting the For Iterator loop, connect an Outport block to capture the final state of your vector.

Example Configuration

- In your Assignment block, you might set it up as follows: - Inputs: - First input: Current state of `Vector` - Second input: New value based on conditions - Assignments in your logic:

      if iteration == 1
        Vector(1) = 1;
      elseif iteration == 2
        Vector(2) = 3;
      end

By using this approach, you minimize memory usage since only specific elements are updated rather than copying and reassigning the whole vector.

Hope this helps.

[John]

Hi @Umar,

Thanks a lot for the answer. I had tried a solution i believe very close to yours an hour ago, which I felt like there is no more optimal implementation with how Simulink allows. I have pasted the snapshot in the bottom of this reply.

At the same time, it is not clear to me couple of your comments if you could elaborate.

4. "If none of these conditions are met (i.e., for iteration > 2), simply pass through the current value of that element without making any updates." Can you explain how to "pass through the current value" in your mind?

5. "Ensure that after each update, you connect the output of your Assignment block back into itself or use it as an input for subsequent iterations, allowing it to carry forward any changes made during previous iterations". Do you mean using a memory block to send back the whole vector from output Y back to Y0? As with this document, https://www.mathworks.com/help/simulink/slref/iterated-assignment-with-assignment-block.html, I don't think it is necessary

[Umar]

Hi @John,

Please see attached screenshot when clicked the link below provided by you in your comments. It mentions “file does not exist”.

https://www.mathworks.com/help/simulink/slref/iterated-assignment-with-assignment-block.html

After going through your comments, to efficiently update specific elements of a vector in Simulink without copying the entire vector, you can utilize the For Iterator Subsystem along with an Assignment block. Here’s a concise breakdown of the process:

Model Setup: Create a new Simulink model and add a For Iterator Subsystem.

Vector Initialization: Use a Constant or Inport block to initialize your vector as [0, 0, 0].

Assignment Block: Insert an Assignment block to update specific vector elements based on the iteration index.

Conditional Logic: Implement a Switch block to determine which vector element to update. For instance, if the iteration index is 1, update Vector(1); if it’s 2, update Vector(2). For iterations greater than 2, simply pass the current value through without modification.

Output Connection: Connect the output of the Assignment block back to the input for subsequent iterations, ensuring that changes persist.

Regarding your questions, "passing through the current value" means that if the condition is not met, the output of the vector element remains unchanged. You do not need a Memory block; simply connect the output of the Assignment block directly back to the input of the vector for the next iteration. This approach optimizes memory usage and maintains the integrity of your vector throughout the loop.

Hope this helps.

[John]

Hi @Umar,

Can you please share a screenshot of the Simulink implementation that you are suggesting or attach the model itself?

Thanks,

[Umar]

Hi @John,

I do apologize since I have access to Matlab mobile but could not afford Simulink. I can provide the links to blocks listed below which will help you out to understand by implementing the model.

Inport block

https://www.mathworks.com/help/simulink/slref/inport.html

Assignment Block

Assignment block

Switch block

Switch block link

[John]

Hi @Umar,

"You do not need a Memory block; simply connect the output of the Assignment block directly back to the input of the vector for the next iteration. This approach optimizes memory usage and maintains the integrity of your vector throughout the loop"

Do you mean "input of the vector for the next iteration" as input Y0 or input U of the assignment block? We cannot do that for input Y0 without a memory block as it will create an algebraic loop. We cannot do that for input U because input U is a scalar while output of the assignment is a vector.

Sorry to hear that you don't have Simulink. Can you please try Simulink online here? https://www.mathworks.com/products/simulink-online.html. It allows free usage of 20 hours per month.

[Walter Roberson]

https://www.mathworks.com/help/simulink/slref/assignment.html

Assignment Block in Conditional Subsystem

If you place an Assignment block in a conditional subsystem block, a hidden signal buffer (which is equivalent to a Signal Copy block) is inserted in many cases, and merging of signals from Assignment blocks with partial writes can cause an error.

However, if you select the Ensure outport is virtual parameter for the conditional subsystem Outport block, such cases are supported and partial writes to arrays using Assignment blocks are possible. See Ensure Output Port Is Virtual.

The link describes ensuring the output port is virtual, which bypasses the Signal Copy block, as you requested. Unfortunately to me the documentation is not clear as to what it means to have a virtual output port. The examples show that it does have an effect on output, but at the moment I do not understand what the difference in output is.

[John]

Hi @Walter Roberson:

My understanding on the virtual outport is limited but I am putting below so that you are welcome to point out my mistakes if having

1. In specific cases, such as in the example at https://www.mathworks.com/help/simulink/ug/ensure-outport-is-virtual.html, we could see virtual and non-virtual result in different values coming out of the logics
2. There are many other cases, or I might say most of the cases, the results are not different
3. The default setup is always non-virtual and in many cases, we probably often ignore the fact that it is non-virtual without further analysis. I think because of 2, it is acceptable
4. There are some specific logics that Simulink doesn't allow non-virtual, and we have to set it as virtual. For example, I use Simulink examle openExample('simulink/PartialWriteSignalsWithMergeBlockExample') and then modify the outport from virtual to non-virtual and it caused the following error: "The signal from 'ex_partial_write_single_merge/Run_Process_SubSystem/Assignment' output port 1 is required to be persistent, hence this signal cannot be connected to a Merge block".

I am looking forward to further discussions on this topic.