Help understanding how C2000 Cmpa values updates during EPWM Trigger Events

Hello everyone, i am actually using the C2000 microcontroller TMSF28388D of Texas Instrument and i am actually struggling to understand how the EPWM module and SOC trigger work. My aim is to realize a PI Controllerfor a H bridge Converter and i want to read voltage value from the ADC module when the TBCTL is equal to 0 so essentially at the start of my carrier signal then i want,based on this value,evaluate the new cmpa value in order to reach my desider reference. What i don't understand is how this temporally work. When the event TBCTL = 0 happens, I read the value and in the same moment i evaluate this in order to find my desider new cmpa value, but later when this value will be updated in my EPWM registers? if i use the shadow mode i can update the register, if i understood good, the zero event after, so essentially one period later, is it right? But this means that i can acquire just one ADC value and to update the cmpa just one time for switching period? if i want for example,using Up/down mode, to acquire ADC values two times in a period so in TBCTL = 0 and TBCTL = PRD by creating two differents interrupt and ISR, how this will temporally work? I mean i start from 0 so the first event soon occured, i evaluate the cmpa and when this value will be updated? if i updated it immediately, i will have the desidered duty just for 1/4 of the period cause the TBPRD happens at Tpwm/2 in up/down mode and later when TBCTL = TBPRD i should read the adc value again and evaluate a new duty cycle? what should i expect from the ADC voltage acquirements,after applying the first cmpa value but only between 0 and TBPRD? For example settling a 50% desired duty, since my duty is applied only for half a period i should expect a 25% of the duty? Can you please solve my doubts if possible making an example of how all this should temporally work and happen? I should use the first event to read the value and the second one to update, or just reading and evaluating the control value for each TBCTL event? Thanks in advice for the support!

Answer 1

[Umar]

Hi @Gianluca,

I’ve gone through your detailed comments and will address each of your doubts step by step, focusing on how the ePWM, SOC triggers, ADC sampling, and CMPA register updates line up in time. I’ve also added references so you can follow up with MathWorks and TI documentation.

1. When CMPA gets updated after TBCTL=0 event

You are right that if you use shadow mode, the value you write in the ISR is not immediately applied. The actual transfer from the shadow register to the active CMPA register occurs at the event configured in the `CMPCTL.LOADAMODE` setting (TI Technical Reference Manual [SPRUFN4], section on Compare Unit).

• If set to Zero, the transfer occurs only when `CTR=0`.
• If set to PRD, the transfer occurs when `CTR=PRD`.
• If set to Both, it transfers at both events.

So, if you write CMPA at `CTR=0` but the load mode is Zero, it won’t become active until the next `CTR=0`, i.e. one PWM period later. With PRD, it will become active half a period later.

2. Updating CMPA only once per period

With shadow mode, yes, a single ADC sample tied to `CTR=0` will update CMPA once per full PWM period. To achieve two updates per period in up/down mode, you can use both `CTR=0` and `CTR=PRD` events (see TI TRM, ePWM – Compare and Action Qualifier sections; also MathWorks “ADC-PWM Synchronization Using ADC Interrupt” example).

• At `CTR=0`: trigger ADC, compute new CMPA, and configure the load mode to apply the update at `CTR=PRD`.

• At `CTR=PRD`: trigger ADC again, compute a second CMPA, and configure the load mode so it updates at `CTR=0`.

This way you get one duty update for each half of the PWM cycle.

3. Timing in up/down mode with two ADC triggers In up/down mode, a full PWM period is `2 × TBPRD`. The two critical points are `CTR=0` and `CTR=PRD`. By using both, you can have:

• First ADC sample and CMPA update taking effect in the second half of the current cycle.

• Second ADC sample and CMPA update taking effect in the first half of the next cycle.

References: MathWorks C2000 Blockset documentation on ePWM types and SOC triggering, TI F28388D TRM (time-base counter and compare unit).

4. Concern about getting only “half duty” (e.g., 25% instead of 50%)

That happens if your CMPA update only affects half of the PWM cycle. For example, setting 50% duty but only for one half results in an average of 25% across the full cycle. By staggering the load events as described above, you ensure the intended duty applies to each half-cycle consistently.

Reference: TI TRM, ePWM chapter (examples of up/down counting and duty cycle calculation).

5. Practical approach

• Configure two SOC triggers: one at `CTR=0` and one at `CTR=PRD` (MathWorks C2000 ADC block supports this).

• Use their ISRs (or tasks in Simulink) to compute the CMPA shadow values.

• Set the load mode carefully: ISR at `CTR=0` → load at `PRD`; ISR at `CTR=PRD` → load at `ZERO`.

• This way, every ADC measurement directly influences the following half-cycle duty.

References: MathWorks “C2000 Peripheral Blocks: ePWM and ADC” documentation; TI SPRUFN4 (ePWM Compare Unit, ADC SOC Trigger section).

In summary:

• Shadow updates always wait for the configured load event.

• With careful use of both `ZERO` and `PRD` load events, you can achieve two ADC-based CMPA updates per PWM period in up/down mode.

• This prevents the “half-duty” averaging issue you were worried about.

For detailed guidance, I recommend:

MathWorks C2000 Blockset Example: “ADC-PWM Synchronization Using ADC Interrupt” (shows ADC trigger from ePWM and updating duty).

TI TMS320F28388D Technical Reference Manual: ePWM section, especially Time-Base, Compare, and Shadow Register subsections.

I hope this clears up the timing relationship and gives you a working strategy for your PI controller with the H-bridge.

[Gianluca]

Thank you very much you have been very clear.

Best regards