zedboard fpga in loop
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irem on 20 Aug 2015
Commented: Eduardo Flores on 29 Nov 2020
Hello, Has anybody used zedboard in fpga in loop simulation? If so are there any documents or explainitions? Thank you
Tao Jia on 24 Aug 2015
There is a generic tutorial at: http://www.mathworks.com/help/hdlverifier/examples/verify-hdl-implementation-of-pid-controller-using-fpga-in-the-loop.html?prodcode=ES&language=en.
Note that zedboard only supports JTAG connection with the host when using FPGA-in-the-Loop, while this tutorial was designed for both Ethernet and JTAG connection. You just need to following the instructions specific to Xilinx JTAG.
To run this demo, you need Xilinx Vivado.
Hey @Irem, did you managed to solve the Device arm_dap_0 is not programmable error?
Antti Wredfors on 23 Sep 2015
I have some diffuculties with new 2015b release too. It's a litle bit same like previous post. The tcl file will not download bitstream correctly.
HDL Workflow advisor can sometimes program Zedboard, but usually it does not! If I use Vivado 2014.4 to download bitstream then it works. (Without tcl functions)
What I discovered was that "vivado_download.tcl"-file is not fully correct at this Vivado 2014.4 release. With Simulink 2015a and Vivado 2014.2 this works always correctly. But not anymore with new releases.
Original vivado_download.tcl file uses command "current_hw_target [get_hw_targets *]". If I remove this line from tcl file, then this works perfectly.
Is there any soutions for bitstream download issues?
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