Is it possible to test a HDL design with multiple clocks using FPGA-in-the loop and Simulink?
11 views (last 30 days)
Show older comments
I would like to test a design using FPGA-in-the-loop simulation. ¿Is it possible to test a design that contains multiple clocks with different frequencies? (200MHz,100MHz,50 MHz and 25 MHz).
Tao Jia on 3 Jul 2016
FPGA-in-the-Loop does not support multiple asynchronous clocks. If all your clocks are synchronous, i.e., they are derived from the same clock, it might work, but you'll probably have perform some manual modification to the FPGA-in-the-Loop generated FPGA project to make that work.
Find more on FPGA-in-the-Loop in Help Center and File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!Start Hunting!