how to generate an "inout" port by Simulink HDL coder?

I want to generate a blackbox interface for a subsystem to an existing HDL code. there are some "inout" ports in the HDL code,but I don't know how to generate such kind of port by simulink. Pls help me ~~~~ thanks a lot !

Answer 1

[Kaustubha Govind]

I don't believe this functionality currently exists. Please contact Tech Support to submit a feature request.

[Zhixun]

Does this functionality exist now?

Answer 2

[Kiran Kintali]

In 2014a we have added support for INOUT ports in HDLCoder.

Bidirectional port specification:

You can specify bidirectional ports for Subsystem blocks that have Architecture set to BlackBox. In the FPGA Turnkey workflow, you can use the bidirectional ports to connect to external RAM. In the generated code, the ports have the Verilog® or VHDL® inout keyword. However, Simulink does not support bidirectional ports, so you cannot simulate the bidirectional behavior in Simulink. Please see documentation for this feature in HDLCoder inR2014a. This is a HDL code generation only feature and you should be able to specify a port to be bidirectional through right-click HDL properties.

Hope this helps.

[Guillaume]

Please, could you tell me if HDL coder can give a RAM with in and out bus in MATLAB code :

persistent hRam; if isempty(hRam) hRam = ufi(zeros(140,1),32,0); end

if load == 1 hram_temp = input; hRam(indice,1) = hram_temp; else hram_temp = hRam(indice,1); output = hram_temp; end

This code does not give RAM but combinatorial VHDL.

Answer 3

[Kiran Kintali]

this should work. thanks

 % codegen -config:hdl -args {ufi(0,32,0),true,uint8(0)} read_or_load_ram

 function output = read_or_load_ram(input, load, index)

 persistent hRam; 
 if isempty(hRam) 
    hRam = ufi(zeros(140,1),32,0); 
 end

 if load == 1 
    hram_temp = input; 
    hRam(index) = hram_temp; 
    output = hram_temp;
 else
    hram_temp = hRam(index); 
    output = hram_temp;
 end
end