Kiran Kintali
MathWorks
Professional Interests: Signal Processing, FPGAs and ESL Design
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Content Feed
HDL code for 'findpeak' function
please find attached a pulse detector example. You can find a similar thread here.
15 days ago | 0
POW2(A) is not supported when A is a FI object.
You are using Variable dimensions and the coding style is not suitable for HDL Code generation or FPGA/ASIC synthesis. Few...
28 days ago | 0
POW2(A) is not supported when A is a FI object.
Please share your design.m and testbench.m and MATLAB to HDL project file. Thanks
1 month ago | 0
Error while using HDL coder
Thanks for sharing the reproduction steps. Classes in MATLAB are not supported for fixed-point conversion. The cryptic error a...
1 month ago | 1
want to convert my simulink model to VHDL using HDL workflow advisor
Does pulse detection example from his thread give you some clues on your approach the problem? https://www.mathworks.com/matlab...
1 month ago | 0
Error while using HDL coder
Can you share your reproduction steps? It will help with the investigation. Design.m <algorithm you are trying to convert to C/...
1 month ago | 0
Control the gain variable inside the generated IP block
please review this example Getting Started with Targeting Xilinx Zynq Platform https://www.mathworks.com/help/hdlcoder/ug/gett...
2 months ago | 0
Hello. I'm traying to generate un HDL code from matlab user-definded function algorithm and got an error about function specialisation that I didn't understand.
Can you share a sample design.m, testbench.m and project file used for fixed point conversion? Thanks
2 months ago | 0
HDL Code Generation for Hit Crossing Block
HDL code generation is currently not supported for Hit Crossing block. However Hit Crossing block functionality can be implement...
2 months ago | 0
| accepted
Question
HDL Code Generation for Hit Crossing Block
HDL Code generation is not supported for Hit Crossing block. How do you model this block for HDL Code generation using basic blo...
2 months ago | 1 answer | 0
1
answerHDL Coder error: Evaluation on class hdldefaults.IntegerDelay failed with the error message Simulink:Engine:RTI_REDUCED_BLOCK...
Can you share your model? Thanks.
2 months ago | 0
MATLAB function block doesn't generate synthesizable HDL.
The issues you were facing are related to mix of incompatible single and double types in the model causing compilation issues ...
2 months ago | 0
| accepted
MATLAB function block doesn't generate synthesizable HDL.
An operator or a block in Simulink can support all floating point types (for input, output and intermediate settings) that are...
2 months ago | 0
simulink_hdl_coder says unable to check out license, even though the tool has that license checked-out
Please reach out to https://www.mathworks.com/support/contact_us.html Thanks
2 months ago | 0
What are MIL, SIL, PIL, and HIL, and how do they integrate with the Model-Based Design approach?
In a HIL setup, Simulation of plant models can be pretty compute intensive and challenging for CPU based simulators. Simscape t...
2 months ago | 0
MATLAB function block doesn't generate synthesizable HDL.
https://www.mathworks.com/help/hdlcoder/release-notes.html R2019b New Features, Bug Fixes Model and Architecture Design HDL ...
2 months ago | 0
Error in using rate transition for multiple clock domains
Some init scripts might be missing when I ctrl-d the model. For example I get the error. Variable 'activeLines' does not exis...
2 months ago | 0
How to create a single dsp model that can be used for different fpga vendors (HDLcoder)
You can generate HDL code from variants. Attached is an example of the variant subsystem model using basic variant features. ...
2 months ago | 1
| accepted
R2020b Update 6 Crashes After Opening HDL Workflow Advisor
This is helpful. This looks like error is happening during model compilation or simulation and unrelated to code generation. I w...
3 months ago | 0
R2020b Update 6 Crashes After Opening HDL Workflow Advisor
This is not expected behavior. To workaround the issue can you reach out to https://www.mathworks.com/support/contact_us.html? ...
3 months ago | 0
How to assign the name of a (multiple) port while using HDL Coder generate RTL from simulink
Resource Sharing For Area Optimization Additional Help for Sharing Factor https://www.mathworks.com/support/search.html?q=...
3 months ago | 0
MATLAB function block doesn't generate synthesizable HDL.
I am attaching R2018a version of the model for viewing the contents of the MATLAB function. I recommend upgrading to latest rele...
3 months ago | 0
MATLAB function block doesn't generate synthesizable HDL.
Try the attached sample model which shows how to MATLAB function block with floating point single precision code using native fl...
3 months ago | 0
HDL coder error empty simulink object
>> mlhdlc_demo_setup('sysobj') you can see some of the examples in the product. >> ls mlhdlc_sysobj_ex.m mlhd...
3 months ago | 0
How to create a single dsp model that can be used for different fpga vendors (HDLcoder)
>> But it won't load in my matlab version R2019b >> openExample('hdlcoder/DesignForEfficientDSPBlockMappingExample') Attached ...
3 months ago | 0
How to assign the name of a (multiple) port while using HDL Coder generate RTL from simulink
>>As you see, input port of Demo is automatically expanded into in_0, in_1, in_2. My question is can the input name in RTL chang...
3 months ago | 0
Min and Max error while using HDL-Coder
Can you share your MATLAB project file with DPCM_Func.m entry point function and input type definition? https://www.mathworks.c...
3 months ago | 0
How to store the output of a repeating function (Matlab Function Block Simulink) ?
>> Do you have an idea how to detect multiple peaks not just one ? Can you consider Multiple enabled delays in a cascaded fashi...
3 months ago | 0
Unrecognized function or variable 'vsim'.
Based on your snapshot of ver command above it looks like you do have access to HDL Verifier. Try using one of the following c...
3 months ago | 0
| accepted
How to store the output of a repeating function (Matlab Function Block Simulink) ?
>> makehdl('pulse_detector_v4_with_index/Pulse Detector') ### Generating HDL for 'pulse_detector_v4_with_index/Pulse Detector...
3 months ago | 0
