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i want to implement 5G NR OFDM system in verilog code using HDL coder
https://www.mathworks.com/help/soc/ug/5g-nr-intro-downlink-signal-detection-rfsoc.html This example shows how to deploy a 5G ...
4 days ago | 0
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentati...
29 days ago | 1
Interface with the Deep Learning Processor IP Core (Execution Modes)
System Integration of Deep Learning Processor IP Core This page shows lists the relevant examples https://www.mathworks.com/h...
1 month ago | 0
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Unable to set Synthesis Attribute on Entity using hdlset_param
In the latest release you should see Block and Block Outputs (Signal) related synthesis attributes specification dialogs and t...
2 months ago | 0
Unable to set Synthesis Attribute on Entity using hdlset_param
https://www.mathworks.com/help/hdlcoder/ug/configure-custom-synthesis-attributes-for-simulink-blocks.html HDL Coder allows at...
2 months ago | 0
Deep Learning HDL Toolbox with CycloneV SoC board
Can you consider using the example and extend to DE-10 Nao Kit? https://www.mathworks.com/help/hdlcoder/ug/define-and-register-...
2 months ago | 0
Convert a part of simulink model of my project to VHDL or Verilog code for FPGA
https://www.mathworks.com/help/hdlcoder/simscape-to-hdl.html Simscape Hardware-in-the-Loop Workflow Generate HDL code from S...
4 months ago | 0
Is it possible to change Simulink MATLAB Function Block 1-indexing to 0-indexing?
If possible can you share your model and the version of MATLAB you are using? There are few tricks in MATLAB coding and design...
4 months ago | 0
| accepted
Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version?
HDL Coder Language Support VHDL, Verilog, and SystemC HLS Language Support The generated HDL code complies with the following...
4 months ago | 1
When I click on "View Code" after generating Verilog code in HDL Coder, the program doesn't respond.
https://www.mathworks.com/help/hdlcoder/ug/traceability-report.html If you are facing issues with code view please reach out to...
4 months ago | 0
| accepted
HDL Code Generation Issue – Exceeding IO Pin Count Threshold & MATLAB Freezing
If the generated HDL DUT code results in unreasonable IO, it may eventually lead to failure to meet pin constraint during synthe...
5 months ago | 0
SigmoidLayer wont work while implementing on ZC706
Thank you for reporting this. Development team is able to reproduce the issue and will post an update soon.
5 months ago | 0
Simulink HDL Coder error when generating
This is an unexpected error handling the if/elseif control structure. Please reach to tech support or share your model here. We ...
5 months ago | 0
How can we tune the Discrete integrator of the HDL Coder for second order generalized integrator for FPGA
Can you share the model here or via tech support? Thanks
5 months ago | 0
| accepted
Can't register a custom board for the HDL Deep Learning Toolbox
>> Does MATLAB have the option to register a custom board? Yes, You can see the doc here https://www.mathworks.com/help/hdlcode...
5 months ago | 0
How do I configure HDL Coder so that it recognizes my Vivado version?
Please review this post that is relevant here. https://in.mathworks.com/matlabcentral/answers/518421-which-versions-of-vivado-a...
5 months ago | 0
| accepted
What's the most suitable Vivado version for Matlab 2025a
This example shows how to model, partition, and deploy a design that leverages the processor, FPGA, and AI Engines on a Versal d...
5 months ago | 0
| accepted
MATLAB HDL-Coder: Expression could not be reduced to a constant.
Is hwconst an input variable (creates hardware interface pins) or just a non-tuanble constant parameter passed into the design...
5 months ago | 0
| accepted
Troubleshooting Signal Logging in SDI for FPGA Outputs in Speedgoat Motion Control HDL I/O Blockset
Klemen, Thanks for reporting this. Our support team at Speedgoat is reviewing the issue and respond here shortly.
6 months ago | 1
How to resolve unsupported functions in MATLAB HDL Coder?
Happy to assist you with your MATLAB to HDL workflow. Attached is a sample zip file with the code for the attached functions (us...
6 months ago | 0
Error evaluating parameter. Dot indexing is not supported for variables of this type.
Can you please share your model here or reach out to tech support? The following message is not expected and a better message ne...
6 months ago | 0
Matlab for my needs
https://www.mathworks.com/help/hdlcoder/examples.html https://www.mathworks.com/help/hdlcoder/run-and-verify-generated-ip-cor...
7 months ago | 0
Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project?
Generating an IP core wrapper for the HDL Coder generated code is the best way to integrate your algorithm into an existing vi...
7 months ago | 1
Ultra RAM on True Dual Port RAM
Please do attach your sample model as a test case. This is a known issue and HDL Coder R&D team have reported the issue to Viva...
7 months ago | 0
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Using fixed FPGA capacity for a variable number of Simulink signal channels
Have you considered tunable parameter usage in HDL Coder? https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-...
7 months ago | 0
HDL Coder "Error using find Too many input arguments."
Based on the error message this issues seems to be related to report generation infrastructure failure. The issue is resolved in...
8 months ago | 0
Do the additional delays added by adaptive pipeline distroy the alignment between signal paths?
Please share your release. Adaptive Pipelining is an optional feature. When enabled it tries to improve timing of your design. ...
8 months ago | 0
Deep Learning HDL Toolbox + Quartus Pro 23.3
Please check the HDL Coder supported version of Intel Quartus with R2024a and R2024b releases. https://www.mathworks.com/help/r...
9 months ago | 0
how to download the third party support package file "xilinx linux binaries"
What version of MATLAB are you using? Please do not hesitate to reach out to tech support.
9 months ago | 0
Seeking Guidance on Auto-Generating Verilog Code for ASIC Simulation with HDL Coder and Deep Learning HDL Toolbox
Classify ECG Signals Using DAG Network Deployed to FPGA This example shows how to classify human electrocardiogram (ECG) signal...
9 months ago | 0