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Kiran Kintali

MathWorks

Last seen: 2 days ago Active since 2011

Professional Interests: Signal Processing, FPGAs and ESL Design

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Answered
how to convert matlab code in VHDL ? which tool boxes to download?
You need to partition the MATLAB code into design and testbench files and create a HDL Coder project. Try a sample MATLAB to HD...

2 days ago | 0

| accepted

Answered
How i can import an existing IP Core in Vivado in Simulink as block?
These links show how to integrate custom RTL code into a model targeted for HDL code generation using HDL Coder https://www.mat...

2 days ago | 0

Answered
HDL coder fails generating wavelet denoise function
Support for C/C++ code generation exists for wdenoise. I have reported the HDL Code Generation request for this function to dev...

11 days ago | 0

Answered
Using std_logic_vector(0 downto 0) in HDL Coder
Unfortunately this coding style switch is not currently available. I have communicated this request with the development team. ...

11 days ago | 0

Answered
error in dlhdl.buildProcessor(hPCNew) step
Can you share the version of MATLAB you are using?

18 days ago | 0

Answered
Explanation of "Assertion failed port already connected to signal error" when generating using HDL Coder?
We are unable to reproduce the issue on our end with the attached models. Please reach out to support for additional help on thi...

18 days ago | 0

Answered
how to create bit from image to feed as input to xilinx multiplier block in system generator
Check this example on how to convert a frame to a sample and feed the sample into FPGA >> mlhdlc_demo_setup('heq')

19 days ago | 0

Answered
Unable to create project in xilinx vivado 2015.2 from simulink using hdl workflow adviser,Getting error [12-172],how can get pass this?
https://www.mathworks.com/help/hdlcoder/ug/using-ip-core-generation-from-matlab.html Generate Custom HDL IP Core for Blinking L...

19 days ago | 0

Answered
hdl coder IO buffer error
Answering the question without access to the model or the full context here. You could consider enabling the resource utiliza...

19 days ago | 1

Answered
HDL Coder removes I/Os of a model reference when they are terminated inside the model reference
Remove Redundant Logic and Unused Blocks in Generated HDL Code https://www.mathworks.com/help/hdlcoder/ug/remove-redundant-lo...

19 days ago | 0

Answered
Generate HDL Code for Simscape Models
The model does not show failures in HDL Coder R2020a and R2020b releases. Can you please sure additional information or reach o...

20 days ago | 0

Answered
Inferring RAM zero index issue
Can you MATLAB code (dut.m) and a Testbench (dut_tb.m) and the project file with MATLAB to HDL codegen settings? This example...

23 days ago | 0

Answered
Explanation of "Assertion failed port already connected to signal error" when generating using HDL Coder?
This is an unexpected internal error. Reported to the development team. Can you let us know what version of MATLAB / HDL Coder...

24 days ago | 0

| accepted

Answered
Generate HDL Code for Simscape Models
Can you share your Simscape model?

25 days ago | 0

Answered
Generating HDL from a Random Number Generator
The mask on the uniform generator has sample time and seed parameters. The uniform generator produces uint32 ...

28 days ago | 1

| accepted

Question


Generating HDL from a Random Number Generator
How do I model Random Number Generator suitable for HDL Coder?

28 days ago | 1 answer | 0

1

answer

Answered
Multiple outputs from HDL block in simulink
https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-axi4-stream-interface-in-zynq-workflow.html Getting Started wit...

1 month ago | 0

Answered
Activation Network Connection Failed in Hardware Setup
Contact support@mathworks.com with reproduction steps.

1 month ago | 0

Answered
Multiple outputs from HDL block in simulink
Can you share your model? Thanks

1 month ago | 0

Answered
How do you make D-FF for HDL coders in simulink?
Hardware Modeling with MATLAB Code MATLAB® design and test bench guidelines for HDL code generation Model for HDL Code Gener...

1 month ago | 0

Answered
HDL code for 'findpeak' function
please find attached a pulse detector example. You can find a similar thread here.

2 months ago | 0

Answered
POW2(A) is not supported when A is a FI object.
You are using Variable dimensions and the coding style is not suitable for HDL Code generation or FPGA/ASIC synthesis. Few...

2 months ago | 0

Answered
POW2(A) is not supported when A is a FI object.
Please share your design.m and testbench.m and MATLAB to HDL project file. Thanks

2 months ago | 0

Answered
Error while using HDL coder
Thanks for sharing the reproduction steps. Classes in MATLAB are not supported for fixed-point conversion. The cryptic error a...

3 months ago | 1

Answered
want to convert my simulink model to VHDL using HDL workflow advisor
Does pulse detection example from his thread give you some clues on your approach the problem? https://www.mathworks.com/matlab...

3 months ago | 0

Answered
Error while using HDL coder
Can you share your reproduction steps? It will help with the investigation. Design.m <algorithm you are trying to convert to C/...

3 months ago | 0

Answered
Control the gain variable inside the generated IP block
please review this example Getting Started with Targeting Xilinx Zynq Platform https://www.mathworks.com/help/hdlcoder/ug/gett...

3 months ago | 0

Answered
Hello. I'm traying to generate un HDL code from matlab user-definded function algorithm and got an error about function specialisation that I didn't understand.
Can you share a sample design.m, testbench.m and project file used for fixed point conversion? Thanks

3 months ago | 0

Answered
HDL Code Generation for Hit Crossing Block
HDL code generation is currently not supported for Hit Crossing block. However Hit Crossing block functionality can be implement...

3 months ago | 0

| accepted

Question


HDL Code Generation for Hit Crossing Block
HDL Code generation is not supported for Hit Crossing block. How do you model this block for HDL Code generation using basic blo...

3 months ago | 1 answer | 0

1

answer

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