Using rate transition blocks in HDL coder

I'm not sure that the rate transition blocks are behaving as I am expecting them to when converting to HDL. For example if I have a producer that is pushing data faster than the consumer needs it, will a rate transition block infer a FIFO in HDL to ensure no data loss? I do have "Ensure data integrity during data transfer" and "Ensure deterministic data transfer (maximum delay)" checked. How does this affect the HDL synthesis?

Answer 1

[Kiran Kintali]

A Rate Transition block does not infer a FIFO in HDL, even when

✔ Ensure data integrity during data transfer and

✔ Ensure deterministic data transfer (maximum delay)

are checked.

Those parameters affect simulation semantics and register insertion, not FIFO generation. HDL Coder only generates bypass registers not storage buffers capable of absorbing rate mismatches.

In single‑clock mode, a timing controller is generated when multiple rates are present in the model to provide clock‑enable signals with the required rate and phase. In mult-rate, multi-clock mode each rate maps to a seperate clock signal; timing controller is optimized where possible.

Please share a sample model for additional support specific to your usecase.

If your question is about automatic insertion of AsyncFIFO here is our roadmap...

• Async HDL FIFO block for AMD devices is part of the official roadmap in the near term. Roadmap includes: Automatically instantiating CDC Macros for async FIFO; Future generic dual‑rate / dual‑port RAM approach for a reusable async FIFO
• Async FIFO features appear in multiple phases: Phase 1: AMD‑focused async FIFO; Phase 2: Generic async FIFO + DRDPRAM improvements and more automation in the subsequent releases.

We will provide examples and demonstrations targeting multi‑clock designs when this is delivered. Please contact technical support for additional roadmap questions.

[John]

Instead of a rate transition block, it seems like I would be better off using a delay block with enable port. For example, if a sensor is sending data every 1 us and a control loop needs the data every 100 us. I can create a signal that will pulse the enable line of the delay block every 100 us. This sounds similar to what you described in single-clock mode with a timing controller generating the clock enable signals. However, when I attempt to synthesize this design, the number of LABs required greatly increases. If I use delay blocks though, the number of LABs used is a lot less.