How to use the dsp.HDLIFFT system object?

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Pablo Medina
Pablo Medina on 21 Feb 2017
Commented: Pablo Medina on 21 Apr 2017
I am developing a symple OFDM modulator. I use QPSK symbols as input for the IFFT block (dsp.HDLIFFT). The problem is that my system is not working correctly, sometimes I receive the expected data and sometimes I don´t. I tested the QPSK alone and It works fine. But, when I put together the dsp.HDLIFFT wiht the QSPK modulador the system suffers the above problem.
Exampl of the problem:
A ===> [QPSK,IFFT] ====> B (CORRECT) 1st Test
A ===> [QPSK,IFFT] ====> C (INCORRECT) 2nd Test
A ===> [QPSK,IFFT] ====> D (INCORRECT) 3rd Test
A ===> [QPSK,IFFT] ====> E (INCORRECT) 4th Test
A ===> [QPSK,IFFT] ====> B (CORRECT) 5th Test
The system works fine sometimes but as you can see above I receive wrong data most of the time.
My system object defination is:
ifft128 = dsp.HDLIFFT('FFTLength',128,'ResetInputPort',true);
My code is something like this:
funciton tx = transmitter(rx)
UART_RX_funcion call
MAIN_FUNCTION call
UART_TX_function call
%%%%%%%%%%%%%%%%%%%%
[outputs] = main_fsm(inputs)
persistent a b c ifft128 ...
if isempty(a)
ifft128 = dsp.HDLIFFT('FFTLength',128,'ResetInputPort',true);
end
switch(state)
state1
state2
state3
end
[yOut,validOut] = step(ifft128,yIn,validIn,resetIn);
  11 Comments
Alireza
Alireza on 3 Apr 2017
You need to have a timing constraint when you synthesize, and make sure that the design meet the timing. Check the clock frequency of your design and create a timing constraint based on the clock frequency. After the synthesis and place and route, check if the design meet the timing.
Pablo Medina
Pablo Medina on 21 Apr 2017
Thanks for the answer I still looking forwar this timming contraint.

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