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Pablo Medina


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Has anyone used the dsp.HDLIFFT system object in a real implementation?
I am trying to use this system object for an OFDM modulator but It seems to not work propertly in the FPGA. So, if anyone has so...

7 years ago | 0 answers | 0

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answers

Question


How to use the dsp.HDLIFFT system object?
I am developing a symple OFDM modulator. I use QPSK symbols as input for the IFFT block (dsp.HDLIFFT). The problem is that my s...

7 years ago | 0 answers | 0

0

answers

Question


Does anyone know why I am getting sometimes wrong data and some time correct data from my FPGA?
I developed a simple OFDM system. Basically, my system receive serial data from my pc. Then It calculates an OFDM simbol which ...

7 years ago | 0 answers | 0

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answers

Question


How exactly Matlab sent bits in a serial communication?
I am using serial communication in orden to send an specific binary secuence. For example: DataBits = [0 0 0 0 0 0 0 1], which r...

7 years ago | 1 answer | 0

1

answer

Question


Does anyone know about state variables in HDL Code Generation?
I receive this error in the HDL Coder Genration stage: hdlcoder:pirudd:NonConstStateInInitialization: State variables must be in...

7 years ago | 1 answer | 0

1

answer

Question


How can I send complex data using serial communication to an fpga?
I developed a UART system for a Virtex 5 Xilinx FPGA. It work fine but I only sent binary data. In the other hand, my main funct...

7 years ago | 1 answer | 0

1

answer

Question


How can I represent a complex type number as a binary type number in order implement a serial communication between my PC and a FPGA?
I developed an UART for HDL Code generation. Because I want to implement a serial communication between my PC and a FPGA. %Ma...

7 years ago | 0 answers | 0

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answers

Question


Why I can´t get ping between a FPGA and my PC in the FPGA-in-the-Loop test?
Features: FPGA = Virtex 5 XUPV5 LX110T IP Host Computer = 192.168.0.3 Board IP Address = 192.168.0.2 MAC Address ...

7 years ago | 0 answers | 1

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Answered
HDL Verifier and FPGA in the loop
hi, I am getting the same error. Did you solve your problem? Could you give me a hint? Thanks, for the future answer.

7 years ago | 0

Question


Does anyone know what this error means? "Failed to receive a control packet from the FPGA target."
Im executing fpga-in-the-Loop simulation from MATLAB. My target device is the Virtex 5 XUPV5 LX110T. Everything looks fine even ...

7 years ago | 0 answers | 0

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answers

Question


Why do I get an error with system object calls in HDL Code Generation?
error: hdlcoder:pirudd:systemobjectmultipleuse: System object methods can only be called once My Code: main fucntion: ...

7 years ago | 2 answers | 0

2

answers

Question


Does anyone could give me a hint about using the dsp.HDLIFFT in my code for HDL Code Generation?
Im trying to generate a OFDM symbol for HDL Code Generation. My code is: %Main function [Xt,validOut] = MODEL(Data_In...

7 years ago | 1 answer | 0

1

answer

Question


Why do i get an error in the Fixed Point Conversion Step?
Error: The function 'HDLIFFT128' contains persistent variables 'ifft128' and has specialization 'HDLIFFT128_s1' associated with...

7 years ago | 2 answers | 0

2

answers

Question


Why do I get this error Code generation does not support display for MATLAB classes. 'dsp.HDLIFFT' is a class. ?
I am trying to call a function, which create dsp.IFFT system object, inside another for HDL Code generation. My Code: %main...

7 years ago | 1 answer | 0

1

answer