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HDL Verifier and FPGA in the loop

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shreyas
shreyas on 2 Jun 2012
Commented: Anas EL-FECHTALI on 20 Jun 2023
Hello All,
I am trying to use FPGA in the Loop (FIL) using HDL verifier and simulink, but I keep getting the error:
Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
My board atlys board and I am not able to get reply from the board when I ping it. Can anyone tell me where I am wrong?
  1 Comment
Walter Roberson
Walter Roberson on 2 Jun 2012
I received your email, but this is not a topic I have experience with.
The MAC address would be 12 hexadecimal digits.
There are different meanings of "ping" in use. The most common meaning requires knowing the IP address of the destination, but does not require knowing the MAC address. An IP address such as 192.168.0.1 would be common.

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Answers (8)

Tao Jia
Tao Jia on 8 Aug 2012
There is a trouble shooting section in the HDL Verifier documentation. Try to see if that one helps you. It's possible a network setting issue.

Pablo Medina
Pablo Medina on 15 Sep 2016
hi, I am getting the same error. Did you solve your problem? Could you give me a hint?
Thanks, for the future answer.

Prashant Funde
Prashant Funde on 3 Aug 2017
If this problem is solved please give me some hint.

LIANG GUO
LIANG GUO on 10 May 2019
id not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
Component: Simulink | Category: Model error

Ricardo Mejia Mertel
Ricardo Mejia Mertel on 15 Oct 2019
Hello, I know the thread is quite old but anyone was able to solve the problem?
best regards,
Ricardo

hbot
hbot on 22 Jan 2021
Edited: hbot on 22 Jan 2021
It helped in my case to readjust Windows network adapter "TCP/IPv4" properties to match the network settings of the evaluation board. Make sure that the subnet number is the same, but the host number is different. For example: PC IP 192.168.0.1, board's IP 192.168.0.2. Try pinging the board in Windows cmd (ping 192.168.0.2) - it must work.
The strange thing is that all connection checks passed in MATLAB (HDL Workflow advisor, vefircation during board's support package installation) with incorrect network settings, only the model simulation didn't run, until I set the correct network IP.

Mohamed BAGHDADI
Mohamed BAGHDADI on 23 Jan 2021
Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
Anyone was able to solve the problem?
PS: I am using Matlab 2019b, altera cyclone IV GX, Quartus prime 18.1 and JTAG Connection
best regards,
  5 Comments
dechen Ai
dechen Ai on 15 Jul 2022
The same with you. Have you resoled the problem?
I am using Matlab 2019b, Xilinx zynq xc7z010clg400-1 FPGA baord, Vivado2017.4 and JTAG Connection.
壹 王
壹 王 on 2 Jun 2023
Hello!I receive the same error information.
I used HS2 JTAG cable, xilinx zynq XC7z020400-2, matlab 2021a. Did any fixed this problem ?

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Anas EL-FECHTALI
Anas EL-FECHTALI on 22 May 2023
i'm using matlab 2022b to coimplemente on xilinx zynq XC7z020 , but i get an error :
Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
Component:Simulink | Category:Model error
Is here someone who had the same issue?
  4 Comments
Anas EL-FECHTALI
Anas EL-FECHTALI on 13 Jun 2023
Edited: Anas EL-FECHTALI on 13 Jun 2023
hello, i solved this issue by respecting matlab vivado compatibility.for matlab 2020Rb you have to get vivado simulator 2020.2, for others:
  • R2023a: Xilinx Vivado 2022.1
  • R2022b: Xilinx Vivado 2020.2
  • R2022a: Xilinx Vivado 2020.2
  • R2021b: Xilinx Vivado 2020.1
  • R2021a: Xilinx Vivado 2019.2
  • R2020b: Xilinx Vivado 2019.2
  • R2020a: Xilinx Vivado 2019.1
  • R2019b: Xilinx Vivado 2018.3
  • R2019a: Xilinx Vivado 2018.2
  • R2018b: Xilinx Vivado 2017.4
  • R2018a: Xilinx Vivado 2017.2
  • R2017b: Xilinx Vivado 2016.4
  • R2017a: Xilinx Vivado 2016.2
  • R2016b: Xilinx Vivado 2015.4
  • R2016a: Xilinx Vivado 2015.2
  • R2015b: Xilinx Vivado 2014.4
  • R2015a: Xilinx Vivado 2014.2
  • R2014b: Xilinx Vivado 2013.4
sencondly, you have to install Hdl verifier support packages , go to Add-ons ---->Get Add-ons in matlab and configurate it. then launch run in your simulink design.
Anas EL-FECHTALI
Anas EL-FECHTALI on 20 Jun 2023
sure, my e-mail :elfechtali.forwork.anass@gmail.com

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