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Answered
HDL Verifier and FPGA in the loop
Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and co...
HDL Verifier and FPGA in the loop
Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and co...
5 years ago | 0
Question
Set up HDL verifier
how can i fix this problem? PS: I work with MATLAB 2019b, Quartus Prime 18.1 & FPGA cyclone IV GX.
5 years ago | 1 answer | 0
