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Issue unexpected output from hdlcoder

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satish morigiri
satish morigiri on 31 Jan 2018
Answered: Tim McBrayer on 31 Jan 2018
Dear All,
I'm trying to make a simple verilog code by using hdlcoder. so I used as the below script and function. but I came across unexpected result when I run the hdlcoder.
The expected data is all 0 in simulation.
Would you please help me how to resolve this problem?
-calc.m
%%Function
function out=calc(u)
dx=1.71;
u = u / 1000;
out = u*dx;
out = floor(out);
end
-test.m
clear
clc
u=3000;
a=calc(u);
u=4000;
a=calc(u);
u=5000;
a=calc(u);
Especially, I got the snippet code from calc_fixpt.v But It does not make sense.
assign out_2 = 4'b0000;
always @(posedge clk or negedge reset_x)
begin : out_reg_process
if (reset_x == 1'b0) begin
out_3 <= 4'b0000;
end
else begin
if (enb) begin
out_3 <= out_2;
end
end
end
From this code, the output is always 0. Would you let me know how do resolve this problems?

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Answers (1)

Tim McBrayer
Tim McBrayer on 31 Jan 2018
This looks like an issue with your data types. Note that your output Verilog code has the output being a 4-bit value. You don't show your input data types, so I don't know if you went through float to fixed conversion, or if the data you are supplying is 4-bit data.
Whichever way you arrived at this data type, the problem is in the line u = u / 1000. Since u is defined as 4 bits, it can only store the values 0..15. When you divide any of these values by 1000, in a 4-bit data type the result is always 0.
Possible fixes:
  • Change the data type to a type that does not always round to 0 when dividing by 1000
  • Change your logic so that you are not redefining your input u, but compute u / 1000 into a separate variable

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