MATLAB as AXI Master

The project with the MATLAB AXI Master jtag IP core assembled, programmed into a chip. When I try to create an object (aximaster object), I see a message - Error using fpgadebug_mex Did not find any Digilent® JTAG cable. Make sure that the cable is connected to your computer. What's the trouble?

Answer 1

[Tao Jia]

Please install the following library:

https://reference.digilentinc.com/lib/exe/fetch.php?tok=6ec654&media=http%3A%2F%2Ffiles.digilent.com%2FSoftware%2FAdept2%2BSystem%2BInstaller%2F2.17.1%2Fdigilent.adept.system_v2.17.1.exe

The Digilent Adept2 library should be automatically installed with Xilinx Vivado. For some reason it didn't work for you, but installing Digilent Adept2 directly should solve the problem.

Answer 2

[Tao Jia]

If you are using KC705, then it should work.

How did you program the FPGA? There is an on-board USB-JTAG port which uses the Digilent JTAG module. This is the one that we support. If you use a Xilinx platform cable to connect to the JTAG header on the board, then it won't work.

Can you double check if the Digilent JTAG cable shows up correctly in the Vivado hardware manager?

[sergey plyukh]

Thanks for the quick response! I program the chip via an on-board USB-JTAG the Digilent module. Programming is successful. In the Vivado hardware manager the Digilent JTAG module is displayed correctly. An error occurs during the creation of the object: mem = aximaster ( 'Xilinx')

Text in the Command Window - Error using fpgadebug_mex Did not find any Digilent® JTAG cable. Make sure that the cable is connected to your computer.

Error in aximaster/openCable Error in aximaster

Answer 3

[Tao Jia]

Can you provide more information on this? What's your operating system? Windows or Linux? What's your MATLAB version? Can you post a screenshot of your Vivado program manager here?

[sergey plyukh]

Hello! My operating system - Windows 7 SP1. MATLAB version - 2017b (version 2018a the same result). Screenshot Vivado program manager attached.

[sergey plyukh]

Screenshot

Answer 4

[Elijah Dewey]

Hello, I too have this issue using the KC705 board. The error received reads, Found incompatible JTAG IP version. Expected version: 1.1. Found version: 33.8. The version changes every time when using the LaunchDataCaptureApp, sometimes from 0.0 to 200. The programming of the board in Vivado is successful and the mem = aximaster('Xilinx') returns the same error as described above. Any tips to fix this would be great. (Windows 10, Matlab 2018a)

[Tao Jia]

I'm suspecting that your FPGA was not programmed with the right bitstream.