Sample on alternate edge of clock. how can sample with respect of alternate edge of clock ?

Hi. I am designing TI ADC and for test now the design is consist on 2-sub channels. when I sample the data, both sampler samples at the same instant (rising edge of clock). however, the 1st sampler should sample at the 1st rising edge and then 2nd sampler should sample at 2nd edge of clock subsequently. right now both sampler samples at the same rising edge of clock. How can both sampler samples on alternate edge of clock ? could anyone please help me in the given problem? it would be appreciated. snap is attached.

Thanks.

[Andy]

Not sure if this would work with your application but if you can differentiate the clock pulse, this gives a positive pulse on the leading edge and a negative pulse on the trailing edge. The samplers can then look for different pulses.

[Sarfaraz Ahmed]

Thank you Andy. No, Its not working according to my application. I think I have to work on multi phase clock generation, As I read some papers, in TI ADC normally multi phase clock principle is applied.