How to assign the name of a (multiple) port while using HDL Coder generate RTL from simulink
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Hi,
I am using HDL coder to generate RTL from simulink.
While in my simulink model, the port is not a single signal but a multiple signal, assume the port name is sig, and it contains 3 signals which shares the same signal path. After RTL generation, HDL coder automatically expand the sig into 3 signals, which are sig_0, sig_1, and sig_2.
My questions is how can I assign the expanded name? I donot like the sig_0, sig_1 and sig_2. In my design, I would like to assign it as sig_x, sig_y, and sig_z.
Thanks a lot!
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Answers (4)
Kiran Kintali
on 5 Aug 2021
Edited: Kiran Kintali
on 5 Aug 2021
>>As you see, input port of Demo is automatically expanded into in_0, in_1, in_2. My question is can the input name in RTL changed into in_x, in_y, in_z (by setting somewhere)?
We do not have _x, _y and _z naming scheme currently. Please reach out to MathWorks support for the naming request. Without going into the solution space the specification of the naming convention that you request can be tricky.
>> How can I share the logic since the 3 paths are totally the same? (In reality, the data path logic could be much more complex than the demo, so logic sharing is quite important)
To enable resource sharing of identical channels as shown in your design you need to use the StreamingFactor option on the subsystem. See the attached pdf file on the usage.
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