Updated 06 Nov 2020
Guidelines for getting started using HDL Coder to generate VHDL or Verilog to target FPGA or ASIC hardware. The document provides practical guidance for:
* Setting up your MATLAB algorithm or Simulink model for HDL code generation
* How to create HDL-ready Simulink models, Stateflow charts, and MATLAB Function blocks
* Tips and advanced techniques for HDL code generation
* Code generation settings for specific FPGA/SoC targets, including AXI interfaces
* Converting to fixed-point or utilizing native floating point
* Optimizing for various goals and targets
* Verifying your generated code
It also includes examples to illustrate selected concepts.
Jack Erickson (2021). HDL Coder Evaluation Reference Guide (https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v3.0.0), GitHub. Retrieved .
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